Electronic Design

3D Graphics Accelerator Core Delivers Workstation-Class Performance

Based on a proprietary tiling architecture that only processes polygons seen by the user on the screen, the GP-1 3D graphics accelerator can deliver workstation-quality graphics at PC prices.

The accelerator comes in the form of a block of intellectual property that designers can embed into a full graphics-controller design. In addition to the tiling technology, the core also performs full-scene antialiasing and employs the company's Giga3D graphics technology to render the 3D images. A fill rate of 500 Mpixels/s when clocked at 125 MHz is possible, while a texel rate of 2 Gtexels/s can be achieved. The ability to only process the visible polygons reduces the core's memory bandwidth requirements by a factor of ten, compared to most other solutions.

Although the core employs the company's proprietary tiling approach, it's compatible with existing and projected 3D applications and application programming interfaces, including Direct 3D and OpenGL. The visibility algorithms used in the GP-1 determine if a pixel will be visible when the final scene is rendered. If it isn't, the core doesn't process any related graphics data. If it is, the computations will be performed. This greatly reduces the amount of processing that the core must do, lowering power consumption. The visibility algorithm also decreases the number of Z-buffer writes and reads, texture fetches, and frame-buffer writes. This reduces the memory subsystem's bandwidth requirements, letting lower-cost and lower-power memories be used with the core.

The full-scene antialiasing removes "jaggies" from the polygon edges and intersections, providing a more realistic image. Each pixel's color value is averaged with those of the adjacent pixels, which results in smooth intersections between polygons after the image has been rendered. The GP-1 core also performs tri-linear MIP mapping, 32-bit color rendering, full triangle setup, Alpha blending, specular highlights, and diffuse shading. A 24-bit Z-buffer interface, a 128-bit-wide internal bus, and interface support for x86 as well as other CPU types are all included on the core.

The GP-1 core is available as either a soft core in Verilog along with C-based simulation models, or as a "hard" core already laid out and optimized for the customer's process. The company also has defined its next family member, the GP-2, which it hopes to sample in the first quarter of this year. It will offer higher performance and more features (a 732-Mpixel/s fill rate at 183 MHz, and 5.9 Gtexels/s). Licensing terms for the cores depend on various factors that the company will discuss on a case-by-case basis. However, the cost of the core on a per-chip basis is expected to be considerably lower than that of other three-dimensional accelerators.

GigaPixel Corp., 2350 Mission College Blvd., Ste. 800, Santa Clara, CA 95054; Henry Choy, (408) 654-8005; Internet: www.gigapixel.com.

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