by Amish Desai
Can MEMS become a mainstream technology? It certainly seems so now that microelectromechanical systems (MEMS) are being integrated with CMOS processes. As this trend continues grow, electronics project teams are on the prowl for design tools to help them exploit the high-potential technology.
Few multidisciplinary tool suites exist to support both MEMS and microelectronics design, and certainly no single software package can offer all of the necessary features. Most designers today use several different pieces of software to accomplish design tasks.
Thanks to the inherent multidisciplinary nature of MEMS, both mechanical and electronic design tools are being used. Unfortunately, there’s a dearth of appropriate layout tools, making the MEMS designer’s job harder.
Deriving from the IC world, rectangles, polygons, and wires are the predominant geometries. Most IC layout tools are 2D, which means that a MEMS designer has to extrapolate the three-dimensionality of the fabricated device, though tools are available to perform the 3D visualisation of the 2D masks.
Mechanical engineering tools, meanwhile, usefully incorporate curves, arcs and circles, enabling physical designers to make beams less fracture-prone, to reduce mechanical stress, and to make fluids mix and flow smoothly. Access to a fast, easy-to-use 3D or cross-section viewer is becoming more important in MEMS design. Further refinement is achieved through finite element analysis.
One of the major differences between MEMS and electronic circuit masks is the lack of design rules, and often, the absence of simple Manhattan-style geometries (Figs. 1 and Fig. 2). Also, in contrast to CMOS microelectronic chips, there’s a greater uncertainty between the simulated and actual performance of a new MEMS device. Fabrication and physical effects typically require intensive experimental testing and a thorough understanding before making further modifications.
Only then are neglected second- order effects added back into the finite element analysis (FEA). For some devices (e.g., micro relays or radio-frequency (RF) switches), the number of cycles to failure and failure mechanisms were only solved through tedious experimental analyses.
INVESTING IN LAYOUT TOOLS
Once the design is optimised, the respective process layers must be laid out, and the subsequent output then sent to highresolution masks. Selecting the right layout tool should be regarded as a critical decision. This investment can be instrumental in reducing mask and design errors, ultimately saving time and money in the manufacturing cycle. Layout tools must meet the obvious requirements: easy to use, compatible with third-party design software, and physically able to render the geometries required.
A MEMS layout tool must be able to draw any shape or form in 2D (if not 3D) space. Circles, arcs, and curves are key. Popular mechanical CAD packages offer complete control of curves, but output into GDS format can be problematic. Some electronics-oriented CAD tools, such as L-Edit MEMS from Tanner Research, offer simple arcs and toruses (circle in a circle), which can be grouped into a complex shape. With these groups, you can easily create hierarchical cells.
The ability to see the hierarchy and perform global edits and revisions becomes crucial in revisioning. A key side benefit of the hierarchical layout is memory and rendering speed. If complex curves are required, then the tool must be able to program custom macros in C to create smart, scalable, and variable T-cells.
The rendering of these complex shapes can cause errors during the tape-out. One important difference in the mechanical (or DXF-based) CAD tools versus GDS-based tools is the enclosure of polygons. In masks for MEMS or semiconductor chips, the drawn shapes are either dark (chrome) or clear (etched chrome). Therefore, all drawn geometries must be closed polygons. Most semiconductor (GDSbased) CAD tools create these closed polygons.
However, in the mechanical domain, where CAD tools are used by architects and graphic designers, zero-width lines and open polygons can be drawn routinely (whether intentionally or by mistake). A mask fabricator tool can’t interpret zero-width open lines. Some error-correcting conversions enable users to merge open lines within a certain tolerance, but they’re not fail-safe techniques. This factor has often been found to be the culprit behind many large problems, which sometimes require the MEMS designer to spend hours re-working the CAD drawings.
To make things worse, MEMS designs often require a challenging geometry: holes in a plate. This “polygon within polygon” essentially becomes an ambiguous shape for the mask interpreter. In mechanical drawing programs, this can be handled by artificially splitting up the form into smaller repeating segments, or by splitting the holes onto a different layer and performing Boolean operations (that is, providing the CAD tools supporting this function). Boolean drawing and layer operations supporting solution, filled objects are the best solution, and can be handled by many electronic CAD tools.
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Once the designer draws these smooth shapes, they must be transposed or “pixelated” onto the mask resolution grid in the final output. Therefore, the ability to raster curves by controlling the number of points on a fine (manufacturing) grid is key, because masks are typically “discretised’” before output. Many mask houses still use older software and hardware with set limits on the number of points defining a polygon in GDS format.
For example, if a 500m-diameter circle is to be fabricated in a 0.5m mask resolution, the points on this smooth polygon’s perimeter will number close to 3000. With a more complex shape, this number can reach about 10,000. Many MEMS CAD tools have algorithms that fracture these polygons into smaller shapes with a user-controllable number of vertices.
The scale range of MEMS designs is often four orders of magnitude, requiring constant zooming in and out of the design, forcing designers to be vigilant about drawing errors. A single polygon feature may be millimetres long, have micron-sized features, and need to be placed in relation to another feature with that same high precision.
The accurate object snapping ability of many mechanical CAD tools has become an indispensable feature in IC drawing tools, particularly for large-scale designs. Typical snaps are to corners of polygons, circle centres, arcs, and object edges, all without requiring the designer to zoom in on the exact location.
CATCHING MASK ERRORS
However, hand-in-hand with large-scale design are the potential for mask errors. As a design progresses and more layers are added, it’s easy to make mask drawing errors. These errors normally stem from either inadvertent movement of an object due to an unnoticed selection, or a screen resolution that doesn’t allow the user to see object separation when zoomed out.
In the IC world, many errors can easily be caught before tape-out. How? By using strict design-rulechecking (DRC) engines, and by enabling better layer transparency through multiple layer rendering options. The ability to “see through” the various layers is very useful when trying to visualise three dimensions in a 2D space.
Regarding DRC, the user can customise very simple rules in today’s IC tools that work on all objects, even at the MEMS R&D level. Rules to check for minimum width and separation between layers, for polygons with more than a certain number of vertices, and for overlaps between userspecified layers, can be established via a check-box-driven system. These files can then be shared across projects to set local standards and minimise errors. With L-Edit’s Interactive DRC option, mask errors are further reduced because DRC violations are displayed and can be fixed in real-time.