Electronic Design

For Analog Circuitry, Smaller Isn't Always Better

For 30 years, electronics engineers have come to expect that the main path to "smaller, faster, and cheaper" products is semiconductor integration. Also, greater integration has been enabled by the move to finer lithographies. There are signs, though, that the push to ever-finer lithography is on a collision course with some fundamental laws of physics and economics. In the submicron age, we are approaching some important physical limitations that will change the tradeoffs engineers make between cost and performance. Through most of the 1990s, analog designers enjoyed "riding the lithography curve" for digital circuits. But in the late '90s, things began to change.

With each lithography shrink below 0.5 µm, the maximum allowable supply voltage also falls. While this is of little consequence to the digital designer, it has enormous significance to the analog designer. Shrinking supply voltages make it more difficult to preserve the analog signal in the presence of inevitable noise. Each new reduction in lithography makes it increasingly difficult for the analog designer. In addition, the move to smaller and smaller geometries results in an increasing cost of manufacturing.

Going forward, electronics engineers must change the way they think about product development. In some cases, analog and digital circuitry cannot continue along the same ever-shrinking path. To meet this challenge, engineers will have to carefully distribute functions among components to optimize designs for efficiency, space, and overall cost. In many instances, two chips will be better than one. The key challenge will be selecting the boundary between these chips. This new design imperative is called "smart partitioning," and it involves several rules of thumb:

  • Recognize that some analog applications can't be made practical at lower supply voltages than at present because of manufacturing economics or the need to drive real-world loads like coaxial cable or twisted-pair phone lines. In those cases, smart partitioning requires separating analog functions onto an appropriate higher-voltage technology and implementing digital functions on the best-available CMOS platform.
  • Consider the interface bandwidth required by a candidate partitioned design. The higher the bandwidth, the greater the power dissipation and greater the electromagnetic interference produced. Smart partitioning minimizes interface bandwidth by putting as much digital processing as possible on an otherwise analog chip so that high-speed data flows don't have to come off-chip. In best-practice designs, the off-chip data flow can be carried as a serial bus, with the further advantage of saving pins.
  • Remember that ultimate chip cost depends in large part on the yield from a manufactured wafer. If integrating an analog function with extreme tolerances into a new chip design lowers the ultimate yield of the manufactured wafer, it may make sense to separate that function and avoid the risk of testability or cost issues downstream.
  • Leverage existing designs when unexpectedly low volumes make creation of an ASIC impractical. Select the highest levels of integration available, and use FPGAs to complete the design.
  • Study the external passive components needed to complete a product. Many can be eliminated by using existing mixed-signal devices that incorporate passives in pursuit of a similar goal.

Smart partitioning doesn't mean that designers will have to go back to the pre-90s model of digital functions on one chip, analog on another, and memory on a third. Component sizes can get smaller, but the economics of finer-scale circuits are growing prohibitive for more and more applications. The situation is analogous to air transport: We can make aircraft that fly faster than sound, but for most of us, it's just not worth the cost.

With that in mind, the design philosophy of smart partitioning should be seen not as an obstacle to design progress, but as an opportunity for effective designers to shine. Smart partitioning frees engineers from merely configuring vendor-supplied components to create new products. It eliminates rote thinking and rote problem solving. Companies that master smart partitioning will differentiate themselves by their design, manufacturing, and software-development talents.

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