ARM and Cadence optimise digital SoC design

Cadence Design Systems and ARM have extended their design chain alliance to benefit their mutual customers. This phase builds on the companies' collaborations on IC design, power management and verification to provide new solutions for application-specific needs. The result is the Cadence Optimisation Methodology Kit for ARM Processors, which helps design teams improve performance, power consumption and area when hardening synthesisable ARM processors that can be synthesised.

The Cadence Kit is intended to simplify the application of Cadence technology so that customers can focus their design resources on differentiation rather than design infrastructure. Cadence Kits address application-specific challenges by combining a verified methodology, packaged in platform flows, with IP and consulting all demonstrated on a representative reference design.

The Kit builds on the silicon-proven ARM-Cadence Encounter Reference Methodology, but also includes: Cadence Encounter RTL Compiler synthesis; First Encounter silicon virtual prototyping; front-end views for the ARM Artisan SAGE-X standard cell libraries for TSMC's 0.13µ and 90nm G processes; and service and support to help designers.

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