Electronic Design

ASIC Technology: Ready To Tackle Its Next Task

Ignore the propaganda. Reports of the ASIC market dying are greatly exaggerated. Suppliers of competitive IC solutions, led by the FPGA vendors, cite various reasons for this design platform's downfall: design starts are down, ASIC NRE costs are too high, development times are too long, and design risk is too great (particularly at 90 nm).

Although ASIC design starts are down, the ASIC market hit over seven times the size of the FPGA market last year, according to Gartner Dataquest. This shows a continued strong demand for ASICs' performance premiums and low production costs. Furthermore, new ASIC solutions, such as structured ASICs, offer similar time-to-market and low-cost development advantages that have been the cornerstone of the FPGA value proposition, while delivering performance that FPGAs can't match.

So where does one draw the line when looking at the options for custom silicon? For cell-based ASICs, the ROI sweet spot will continue to be high-performance, high-volume (500,000+) applications that require the leading-edge performance or the economies of scale that only cell-based ASICs provide. These applications are generally developed by very large OEMs with financial resources to support the million-dollar-plus NREs and large design teams associated with cell-based design. In these cases, FPGAs aren't feasible because the cost per device would be much too high and the logic density too low to achieve the needed performance.

Still, today's designs are mostly in the mid-volume range (10,000 to 50,000 units). Despite this drop in volume for custom IC designs, increased competition has OEMs demanding higher performance and faster time-to-market from design platform vendors. In this environment, companies are gun-shy about committing the development time and the financial and human resources needed to develop a custom IC for an application that may not be successful. This has left IC designers and system architects with a daunting task: deliver high-performance ASICs under considerable pressure to minimize time-to-market and NRE because volumes may not justify large development costs.

Clearly, these market realities eliminate cell-based ASICs in many applications. While some would claim that FPGAs have stepped up to address these applications, FPGA logic density and performance remain far behind ASIC technologies. FPGA-based designs require engineers to settle for lower system clock speeds or use multiple FPGAs. Meanwhile, ASIC technologies now bridge the gap between high-performance, cell-based ASICs and the space traditionally served by high-priced, mid- to high-end FPGAs.

Enter structured ASICs. This new breed of ASIC is built on preconfigured lower metal layers that streamlined design and fabrication. They simplify ASIC design by embedding features such as clock trees, power grids, and design-for-test structures. The preconfigured layers give structured ASICs a signal integrity-aware architecture that greatly reduces the need for signal integrity analysis and design iterations, providing faster design turnaround and shorter fabrication times. These devices offer near cell-based ASIC performance that clearly exceeds the most advanced FPGAs, and keeps NRE costs down. Structured ASIC vendors are also quoting time-to-market figures that are very competitive with leading FPGAs. If an application achieves widespread adoption, OEMs can migrate their structured ASIC designs to a cell-based platform much faster than they could migrate from an FPGA.

A variety of design platforms are available, and each has its place. Cell-based ASICs will continue to be best for high-volume applications, while FPGAs are appropriate for low-volume or lower-performance designs, and prototypes or platforms that require and can live with the overhead of reprogrammability. With the introduction of the structured ASIC, designers making custom chips for a broad range of applications can now enjoy the time-to-market advantages of FPGAs, the performance of cell-based ASICs, and an easy migration path for designs that jump from mid- to high-level volumes. Clearly, the ASIC market has adapted to meet changing design requirements, and is ready to address the next challenges of a continually evolving market.

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