Electronic Design

ASIC/ASSP Industry Faces Midlife Crisis

Middle age takes its toll, be it animate or inanimate. The "application-specific" industry, regarding both ICs and standard products, is no exception. Don't expect any sporty red convertibles, though.

Tough times await as customers expect better performance for the same prices. ASICs will need to change their ways to survive, with designers taking preventative measures in the form of up-front designfor-manufacturing (DFM) rules.

Meanwhile, analysts are calling for new value propositions. The industry also needs to learn to play well with others in the form of mergers, alliances, and collaborative efforts. The costs of foundries continue to rise. And, developers need to refine and find new materials to keep the process shrink alive. The fallout of all these factors will be cost-cutting measures, ultimately leading to layoffs.

Value Propositions Must Change
Research firm Gartner believes the ASIC/ASSP industry needs to change its value proposition or face the consequences. That's because margins and design opportunities are shrinking while the industry consolidates its resources.

Take the DVD market. The average selling price of DVD recorders has dropped from about $525 in 2002 to around $125 now, and it will continue to fall to the $50 mark by 2010. Yet design costs have soared from a few million dollars to over $10 million today and are expected to reach over $30 million by 2010.

The non-recurring expenses (NRE) for ASIC/ASSP designs drive up costs as process technology shrinks to 65 nm now and 45 nm soon. Meanwhile, customers demand more features as companies attempt to penetrate more global markets with the same product.

In other words, DVDs now must handle several types of audio and video codecs (with more on the way), such as MP3 and MPEG2. And to work in different countries, DVD recorders must handle several video standards, including NTSC and PAL. It's becoming such a challenge to be profitable in the DVD market that well-known manufacturer Lite-On will stop selling its DVD recorders worldwide because it's seeing too many returned products.

In addition, more features are being integrated into a single chip. With rising design costs, ASSP design starts will continue to decline, dropping from over 6000 in 2000 to about 4000 in 2010.

DFM Or Bust
So, things are changing. For instance, ASIC and ASSP designers now need to consider DFM rules. But how much DFM do they really need to consider?

"One-hundred percent of the responsibility for DFM falls on the designer, because it is the designer who is ultimately responsible for selection of all the elements, from tools to foundry, in the design chain," says Chuck Byers, director of brand management for TSMC. "It is up to the designer to understand the substance of any DFM architecture and to act accordingly to ensure the time-to-ramp, time-to volume, and time-to-money of the design."

ASIC/ASSP designers are trained to understand electronic circuits and the hardware description language required to implement their design. They're also expected to know how to deal with thermal issues and new materials, thanks to the European Union's Restrictions on Hazardous Substances (RoHS) initiative. Going forward, engineers will be expected to know more about manufacturing than ever before.

But being DFM-aware isn't enough. Engineering flows should be revamped to revolve around DFM. TSMC suggests a reference flow in which DFM constraints are employed consistently throughout the design flow, including the cases where external IP is used. Of course, designers must be particularly careful with internal IP reuse. They can't assume a given IP block that once worked with an older process technology will work with the new one.

Once designers determine a reference flow, it's best for them to review that flow with their foundry, IP vendors, packaging vendors, and EDA vendors to ensure everyone is on the same page. In essence, designers are creating a tightly coupled ecosystem that heavily involves their design partners and considers DFM throughout the design process (see the figure).

TSMC took the idea of a DFM-aware ecosystem to the next level by designing a unified data format in the form of a database to help members of the ecosystem ensure DFM compliance at 65 nm. TSMC developed the database format to align lithography process check (LPC), chemical-mechanical-polishing (CMP) analysis, and critical area analysis (CAA) to TSMC's manufacturing data format. This will ultimately empower ASIC and ASSP designers to manage DFM rules in one area, irrespective of the tool or vendor.

For more on DFM rules, see "10 Semiconductor Manufacturing DFM Rules Every Designer Should Follow."

IP Reuse Now and In the Future
Designers involved in ASIC design over a multiyear period have noticed that the number of gates they're responsible for has increased dramatically, and this trend will continue. Typical ASIC engineers may be responsible for around 2 million gates this year. There has also been an increase in the number of IP blocks per ASIC (currently in the low twenties). And, the percentage used from outside sources is around 60% and increasing.

Next, IP is being used less for building blocks, such as digital-to-analog converters (DACs) and ALUs. The same can be said for larger functional blocks like CPUs and DSPs. Instead, IP is finding its way more and more into "killer functions," such as complete video decoders. Gartner suggests that these killer functions are bleeding across multiple markets.

Based on the number of gates per engineer and the trend of using IP for killer functions, engineers are looking at predesigned IP blocks more than ever to make up a good percentage of their design.

"Since IPextreme is purely focused in moving IP between semiconductor companies, we talk to many engineers about their IP needs, and massive design reuse is now the only way chip leaders are getting their products completed," says Trent Poltronetti, vice president of marketing for IPextreme.

"Over the last couple years, we've seen the percentage of IP cores coming from outside the company rise from 40% to 60%," says Poltronetti. "As designers continue to focus on their differentiating expertise, not standards-based functionality, we fully expect externally sourced content to exceed 80% in 2008."

Over 80%? It's difficult to name another industry that builds a product in which over 80% of the design comes from sources outside the company. (Of course, we're talking about design and not bill of materials.)

Changes In 2007 And Beyond
According to Gartner, 2007 will mark the beginning of an era of moderate semiconductor growth, about 9% overall, mostly driven by memory. In particular, the ASSP markets will experience an upswing over the next few years, with cell phones topping the revenue charts and LCD/plasma televisions leading the way in growth. Revenues from consumer electronics will increase 20% over the next two years and then flatten out the following two.

As the cost of new foundries balloons, expect more mergers and alliances, with cost sharing as the goal. Also, more OEMs like IBM will develop technology jointly as another cost-sharing measure, which also helps reduce risk. For example, IBM, Sony, and Toshiba jointly developed the Cell processor over a period of several years and at a development cost of tens of millions of dollars.

The fruits of this co-development are already being seen—the Cell is shipped inside of every Sony PlayStation 3. It's also expected to be deployed in several other applications. For more on the Cell, see "RapidIO Gives DSP ‘Farmers' Something To Crow About."

Based on all of the trends mentioned so far—consumers wanting more features for less money, companies co-developing products, and the need to stay competitive—expect layoffs, product trimming, and overhead trimming over the next few years.

The Future Of Semiconductor Processes
Some foundries will look to offer 45-nm process technology some time in 2008. But that's just the beginning as researchers strive to scale CMOS down to 32 nm and below using highchannel doping, immersion lithography, and a 193-nm laser.

Scaling lower will likely require new lithography technologies, such as extreme ultraviolet lithography. Interconnect also must improve as feature sizes shrink, with designers on the hunt for low-dielectricconstant (low-K) material. In addition, foundries are considering the move to 450mm wafer sizes to roughly double the number of dies per wafer by the year 2012.

Looking further out, researchers will try to pinpoint different materials to replace CMOS while reducing cost and continuing the downward scaling trend. Carbon nanotubes appear promising, as researchers have created basic circuit elements with them. However, they're still a long way away from forming complex circuits. For more information on the future of semiconductor process technologies, see "Back To Nature For Next-Gen Semis."

Let's hope the ASIC/ASSP industry takes a deep breath this year, makes some changes for the better, and regains the strength to live to a ripe old age.

ASIC/ASSP Trends

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish