> The SCS3015 full-function timing signal generator helps simplify the internal timing design of Sonet/synchronous-digital-hierarchy network devices like routers and asynchronous-transfer-mode switches. Implemented within an Actel ProASIC FPGA by 9co, the timing circuit takes advantage of the ProASIC's unique security features, single-chip form factor, and exceptionally low jitter and phase noise performance. As a result, the SCS3015 can offer better than a fivefold reduction in jitter compared to competitive products, enabling reliable application designs.
The SCS3015 is the most complete solution to date within 9co's Stratum 3/3E SCS series. It fully complies with Telcordia GR-1244-Core, GR-253-Core, and ITU-T-G813 standards and features completely hitless reference switching. The chip accepts two reference inputs and provides four synchronized outputs: one with user-selectable frequency, one at 8 kHz, one multiframe sync at 2 kHz, and a built-in timing signal clock at 1.544 or 2.048 MHz. Control is via simple direct hardware I/O. The devices support synchronized, holdover, and free run modes and may be run in master/slave pairs for high reliability.
Samples will be available later this month. Pricing is less than $100 in 1000-unit quantities.
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