Electronic Design

Clock-Generator IP Blocks Let ASICs Deliver Precision Timing

Designers can use a family of precision phase-locked loops (PLLs) available as hard macrocells to deliver system clocks, perform built-in frequency margin testing, and deliver stable clocks for serializer/deseriaizer and video applications.

Developed by True Circuits, these blocks of intellectual-property (IP) macros provide frequency modulation and very high frequency resolution with over 16 bits of control. The TCI-TN90G-HRMPLL macro offers a divided reference frequency range of 6.235 to 400 MHz with reference divider values ranging from 1 to 64.

The macro's period jitter (peak-to-peak) is ±2.5% of the output cycle (worst case), while input-to-output jitter is ±1.25% of the divided reference cycle. It consumes just 7 mA when running at 400 MHz and has a lock time of 500 divided reference cycles. The company's proprietary LockNow! technology can considerably shorten the lock time.

The initial PLLs will be available in the first quarter of 2006. They will target TSMC's, UMC's, and Chartered Semiconductor's 250- to 65-nm processes. They're supplied as GDS II and LVS Spice netlists along with behavioral and synthesis models, library exchange format files, and extensive documentation. Contact the company for licensing fees.

True Circuits Inc.
www.truecircuits.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish