To support the recently released Yellowstone high-speed memory interface, now renamed the extreme data rate (XDR) interface, designers at Rambus Inc. and Integrated Circuit Systems Inc. jointly created a memory interface clock generator. The generator will be offered to the industry through ICS.
The ICS9214 will provide all of the necessary clock signals to control memory chips that incorporate the XDR interface. Four differential clock drivers will be integrated on the chip and housed in a single 28-lead thin-shrink small-outline package (TSSOP). Memories based on the XDR signalling scheme can transfer data at rates of 3.2 to 6.4 GHz per differential signal pair and deliver an aggregate data transfer of up to 100 Gbytes/s. To deliver such performance, accurate, stable clocking like that from the ICS9214 will be required.
The first DRAM suppliers to offer XDR-based DRAMs will be Toshiba Corp. and Elpida Memory Inc. The first DRAM will offer a capacity of 512 Mbits in a 32-Mword by 16-bit configuration. The data interface can operate at 3.2 GHz, with optional speed bins at 2.4 and 4 GHz. At 3.2 GHz, the DRAM can deliver an aggregate data bandwidth of about 50 Gbytes/s, which is approximately eight times faster than today's 400-MHz double-data-rate SDRAMs.
For more information on the XDR signalling scheme, go to www.rambus.com. For the ISC9214, see www.icst.com. For XDR DRAM details, go to www.toshiba.co.jp/index.htm and www.elpida.com.