Collaboration And The X Factor

Kalyan Thumaty, Narian Arora, and Ketan Joshi outline how many in the industry have collaborated to overcome time-to-market pressures caused by the compound effect of delays in design time and yield challenges.

Satisfying time-to-market goals is a crucial factor of a product's viability. Creating designs that can be manufactured is an integral step, especially for the smaller, faster, and increasingly complex ICs that fuel next-generation electronic products. Today's time-to-market issues are a compound effect of delays in design time, caused by longer wire delays and congestion, and yield challenges, caused by a variety of factors.

The X Architecture helps resolve these challenges. By incorporating pervasive diagonal interconnects into an IC design—typically at the fourth and fifth metal layers—the X Architecture reduces the total wiring on a chip. This improves performance and enables the production of increasingly smaller die. The concurrent, dramatic drop in the number of vias results in improved process yield and circuit performance.

A key component in achieving time-to-market goals is collaboration throughout the design chain. This is essential for proving the "manufacturability," economic viability, and ultimately the broad commercial adoption of new manufacturing process. This is no longer the era of "what you see is what you get" design. Instead, producing chips with complex reticle-enhancement techniques, increasingly large data files, and other factors requires the design community to engage with other members of the semiconductor supply chain to ensure the practicability of their designs.

Understanding this, dynamic companies throughout the design-to-wafer supply chain forged a consortium, the X Initiative, to support broad adoption of the X Architecture. This cooperation has led to the first commercial 130nm SoC using the X Architecture. The collaboration also confirmed that the X Architecture can improve yield, as a result of via and die-size reductions, as well as reduce critical area shorts and opens.

As recently as ten years ago, device (transistor or gate) delay had the greatest impact on a chip's performance and integrity. With the advent of nanometre-scale semiconductor process technologies, interconnect delay, or the delay contributed by the wire connecting the devices, has become the most critical contributor to chip timing and reliability. And interconnect—and its associated issues—only increases as design complexity rises. More interconnect equals slower chips, greater power consumption, and fewer chips per wafer. Clearly, making the wires shorter reduces interconnect delay.

However, the nearly universal, artificial constraint of specifying only horizontal and vertical wires on chips—the so-called Manhattan architecture—needlessly adds significant wire length.

Complex, multi-million gate, nanometre-scale chips are implemented using the same underlying algorithms and assumptions that created chips with fewer than 100,000 gates in 1990, after channel routers gave way to area routers in the late 1980s. This facilitated the over-the-cell routing and the sea-of-gates architecture that fueled the ASIC design explosion of the late 1980s and early 1990s.

Clearly these technologies were developed using the assumptions and methods dictated by the computing power available at that time. Since that time, computing technology has improved by more than three times over.

In a typical deployment of the X Architecture today, the fourth and fifth metal layers (referred to as M4 and M5) are each rotated by 45°. On the large scale, M1 to M3 still use the Manhattan format, which simplifies the use of most standard cells, module and memory compilers, and hard IP. On the small scale, diagonals are included on all metal layers.

PCBs have used diagonal wiring for decades. On chips, though, diagonals have mostly been restricted to very short jogs, mainly inside cells. Pervasive diagonal wiring, used on the large and medium scales as well as on short jogs, had not been employed prior to 2004.

Despite the general prohibition of diagonal routing by fabrication design rules, manufacturing limitations are not the fundamental reason for this. The use of 45° wires is fully supported by most current manufacturing technologies. Though making fabs perform as well as for diagonals is harder to do, the yield advantages created by the 30% reduction in via and 20% reduction in wire length is a serious motivation.

These improvements to chip speed, power, cost, time-to-market, signal integrity, reliability, and the probability of a successful first silicon all are compelling customer benefits, and better the manufacturing yield, too. Theoretical discussions led investors to believe that 45° wires in upper layers of metal could be manufactured, but it remained to be seen if there were any issues that would only become apparent in a real manufacturing situation.

To answer this question, the X Initiative was formed to support and drive the proliferation of the X Architecture. This organisation has brought together 42 companies (and counting) from every segment of the semiconductor supply chain to address design for manufacturing issues using the X Architecture as the common platform. In the process, the basis for improved yields was validated as well.

The greatest issues with any new chip technology include the availability of required design and verification tools; photo-mask production and costs; the management of data requirements and data volume through the supply chain; and its impact on yield. To address these concerns, the X Initiative focused on educating the supply chain about the architecture; accelerating fabrication of X Architecture chips; and tracking and promoting the technology's commercial take-up.

In the three years since the inception of the X Initiative, milestones have been achieved through cooperative work. The fabrication of the first X photo masks in late 2001 and early 2002 by Dupont Photo masks and Dai Nippon Printing were followed by lithography demonstrations at 130nm by ASML and Nikon during 2002, 90nm test chip fabrication in 2003, and 65nm in 2004 by Applied Materials. A parallel effort in design produced the first functional chip design by Toshiba in early 2003, culminating in the introduction of the first commercial SoC in X Architecture built by Toshiba in 2004.

The cumulative result is that the "manufacturability" of the design was established early in its development cycle. X Initiative members have shown that it can be manufactured in 180nm, 130nm, 90nm, and 65nm technology nodes using existing production equipment—layout tools, mask tooling and wafer processing—with the same level of line-width control and comparable electrical characteristics as conventional Manhattan layout at the 90nm technology node.

This demonstrates the integration value and economic viability of the X Architecture. Also, CD uniformity and electrical integrity at a 212nm pitch is a good indicator that the X Architecture is scalable to the global wiring level of the 45nm technology node and, consequently, is a viable, long-term strategy for the design community.

In June 2004, Toshiba announced the first production chip implemented using the X Architecture2. The Toshiba TC90400XBG is an SoC for digital television with 2.7 million gates, running at 180MHz, and is targeted to a 130nm process technology with five layers of signal routing. Metal layers M4 and M5 are diagonal.

Toshiba employed a hierarchical design methodology, implementing logic sub-blocks and the chip's top level with the X Architecture, while preserving analogue and digital IP blocks with Manhattan implementation. The resulting implementation is 10% faster and uses 11% less random-logic area than a Manhattan-only version of the same chip.

Perhaps most interestingly, the X Architecture version of the chip was not only faster and smaller, but was implemented more quickly than the Manhattan version. This shows that eliminating substantial amounts of interconnect, thereby simplifying the resources present, offers an opportunity to conceive an entirely new approach to physical-design implementation challenges associated with the interconnect. Aspects affected include routing congestion, interconnect delay, and signal integrity. In short, it has been proved that the X Architecture produces higher quality chips and speeds time-to-market for those chips.

By June 2004, first engineering samples had been tested and confirmed fully functional die and a yield of 80% on one wafer. Volume production is projected for April 2005.

Also in June 2004, PDF Solutions announced the results of a yield study it conducted comparing a Manhattan design with an X Architecture design. The test case was a microprocessor core, with results scaled to achieve the equivalent of a >30mm2 die. After scaling, the test case had 3 million gate equivalents. The test case was implemented in a 130nm process technology. The yields were compared for two process defect densities: ramp and target. The net die per wafer (NDPW) and good die per wafer (GDPW) were compared for the two architectures, using 200/300mm wafers.

The results of this study validated a reduction in vias in the top-level (M4 and M5) metal layers implemented with diagonals. The study also found a reduction in critical area shorts and opens with the X Architecture despite the smaller die. Analysis of pattern densities showed that the X Architecture implementation had reduced density and density hot spots as compared to the Manhattan implementation of the test case. Most importantly, the study confirmed yield improvement of 3% and 1.3% for ramp and target, respectively. The combination of yield improvement and the area reduction afforded by the X Architecture resulted in real GDPW improvement: 23% for ramp and 16% for target on 200mm wafers; 22% for ramp and 15% for target on 300mm wafers

Time-to-market issues are a compound effect of delays in design time, caused by longer wire delays and congestion, and yield challenges. Through the open collaboration of industry leaders, a new IC architecture—the X Architecture—has been proven to not only improve the overall quality of IC design (in terms of circuit speed, die size, via count, and yield), but also speed time-to-market for these ICs. As the semiconductor industry seeks new ways to improve time-to-market for complex nanometre-scale IC and SoC designs, new design architectures such as the X Architecture present a different avenue of exploration that shows great promise.

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