Electronic Design

Cores That Share Chores

Single-chip microcontroller houses a number of Forth processor cores that must cooperate when performing computational tasks.

Reduce the size of a processing core, and usually more can fit onto one chip. IntellaSys took that approach with its Scalable Embedded Array (SEA) architecture, which resembles Parallax's Propeller (see "Eight 32-Bit Cores Take Flight In Multiprocessor Microcontroller," April 13, 2006, p. 62, or ED Online 12235 at www.electronicdesign.com).

However, IntellaSys' SEAforth-24 uses a much simpler instruction set and a nearest-neighbor connection mesh (see the figure). As a result, the SEAforth-24 can cram 24 processing cores into a single chip.

The mesh layout lets adjacent cores exchange data quickly without the complexity or delay of a shared memory system. Moving data through a series of cores between two non-adjacent cores takes more time, though. It increases the design complexity, which suits the SEAforth-24 for some applications but not others.

That's no different than choosing a microcontroller based on its peripheral set for a particular application. Still, designers must understand this new architecture before using it in their designs.

The interconnect is logically similar to the Inmos Transputer from the early 1980s, except that the Transputer had one core per chip. Each core was much more complex than the SEAforth-24 cores. Now, each of the SEAforth-24's cores has its own ring oscillator, creating asynchronous communication between. The interface between cores is a simple buffer register.

Wireless speakers represent one of the SEAforth-24's first applications. Each of the six wireless speakers will have a chip that will handle the wireless communication. The chips also will decode the lossless, streaming audio data.

In this application, each speaker sees the same data stream and decodes its portion for driving its speaker. This simplifies the transmission source and the receiver design, but it does mean that each device must handle information for its speaker at a higher rate. Some of the edge cores handle wireless RF signaling up to 100 MHz directly. There's no off-chip transceiver.

The original experimental design of the wireless speaker system used a pair of multicore chips tied together by their interprocessor communication meshes. Though the final design required only one chip, the initial approach clearly shows how designers could easily connect a very large number of cores.

The SEAforth-24 cores are simple, which helps reduce power consumption. In addition, active cores use very little power (under 20 mw), and inactive cores use almost no power.

An application can deactivate a core when it's waiting for input. The core then is able to start up in one clock cycle. Also, the architecture doesn't support interrupts. Instead, cores are dedicated to peripheral handling, where interrupts are typically employed in conventional architectures.

FORTH FORAY
The instruction set is based on 32 Forth instructions that fit into 5 bits (see "SEAforth-24 Instruction Set," ). The 18-bit words fit three 5-bit instructions and one 3-bit instruction. The 3-bit instruction is a subset of 32 Forth instructions. By the way, one of IntellaSys' main architects happens to be company founder and CTO Chuck Moore, who created Forth.

There are some interesting side effects to packing three or four instructions per word. This allows one or more words to be packaged into a Forthlet code object. Per-core memory consists of 512 18-bit words of RAM and the same amount of ROM. The ROM contains common Forth routines for core-to-core communication and peripheral control for cores on the edge of the mesh.

There's support for a range of typical microcontroller analog and digital peripherals. The 18-bit architecture had some effect on the resolution of these interfaces.

Furthermore, common helper routines are found in ROM. This means the ROM looks more like a 2k instruction block. RAM, on the other hand, is used for Forth code and data.

Also, the instruction buffer acts as a four-instruction cache. Very high-speed micro loops can fit into a single word. One frequent operation is to move Forthlet code objects between cores so they can be executed on a remote corel. This Forthlet support is part of the ROM code.

The chip can boot from a number of sources, including an external serial flash chip. Downloaded code from the flash chip can be propagated through the mesh. External RAM memory support could be added by dedicating a core to the interface.

One of the biggest concerns that will confront most developers is the combintion of new approaches that is provided by the SEAforth-24. Typically, developers are comfortable with a single processor that may run multiple threads with a large amount of shared memory. Nonetheless, it's relatively easy to fit parts of an application into the small cores, even given the memory constraints.

The difficulty arises in optimizing the use of a core or splitting up part of an application from one core when the computational or memory limits are exceeded. Splitting up an application typically will create a ripple effect. That's because application code to core affinity is a major portion of a system design. Luckily, a surprising number of algorithms fits nicely with the IntellaSys mesh architecture, from image processing to encryption and data compression.

Forth Inc., the developer of the Forth SwiftX cross compiler, will provide development tools. Certain specialized tools will address the multicore environment of the SEAforth-24. The chip costs $19.95 in quantities of 1000 units, with discounts for larger volumes.

In addition, expect to see a variation called ColorForth developed by—who else—Chuck Moore. A compact operating system fits in only 2 kbytes of memory, making it ideal for the SEAforth-24. It was started back in 1996.

ColorForth source code is compressed and pre-parsed for fast evaluation. ColorForth was actually used to design and layout the SEAforth-24 chip.

In a text editor, ColorForth looks like code would in a conventional colorcoded editor like Eclipse ,where keywords are a particular color. The big difference is that the latter associates a color based upon a word and its context.

In ColorForth, the programmer specifies the color to specify the use of the word, such as the name of a function definition. An interesting consequence of this approach is that the program must be presented in its color form or the context of the code is lost, whereas conventional programming languages do not care about the actual color a word is associated with.

Developers wanting to take advantage of the SEAforth-24 will definitely need to work in Forth. Depending upon the programmer's background, this will be either a great benefit or an ordeal. In general, Forth lends itself to compact code that will be critical to the success of the SEAforth-24.

The SEAforth-24's multicore architecture lets developers bring a large amount of computing power to bear while potentially reducing the overall power requirements. Letting sleeping cores lie will keep the chip cool and extend battery life. It will be interesting to see if the SEA approach evolves into a higher form or becomes a specialized branch.

IntellaSys
www.intellasys.net
Color Forth
www.colorforth.com

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TAGS: Intel
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