Electronic Design

CPLD Technology Scores A Big Green Zero

Perhaps one of the greater debates among the ancient Greeks involved the status of the number zero. The fundamental question was how something could be nothing, leading to great philosophical and religious debates. One can only fathom a guess as to how the history of the world might have changed had the Greeks stopped arguing and decided the idea of zero might be useful like the Hindus did a few centuries later, around 200 AD.

The idea of nothing being something wasn’t lost on Lattice Semiconductor when it designed its “zero-power” ispMACH 4000ZE complex programmable logic device (CPLD) family (see the figure). Zero power is a bit of a misnomer since the standby current for the devices in the product line ranges between 10 and 13 µA (typical at 1.8 V), and the devices can operate with as little as a 1.6-V supply voltage. Thus, the minimum standby power will range from 18 to 23 µW at 25°C and 1.8 V. In any case, the standby power is so low that the ancient Greeks could have argued that it is zero, which would make the CPLD green in any language. And, the device will afford Lattice customers new design opportunities.

LOW POWER FOR PORTABLES
“With its low standby current, small form factor, and ‘instanton’ operation, the ispMACH 4000ZE family is ideal for handheld and portable equipment such as GPS systems, portable media players, and wireless appliances,” said Stan Kopec, Lattice corporate vice president of marketing. “With over 15 years of experience in the CPLD market, Lattice is uniquely positioned to deliver a product family that serves these emerging applications.”

The ispMACH 4000ZE provides four logic densities ranging from 32 to 256 macrocells. Each device includes an on-chip oscillator, timer, input hysteresis, and per pin pull-up, pulldown, or bus keeper control.

The family also achieves low operating power (90 to 614 µW at 25°C and 1.8 V) with a feature dubbed Power Guard, which lowers dynamic power consumption by selectively disabling unused inputs, preventing internal logic toggling due to unnecessary I/O pin activity. The devices pull this feature off with an enabling multiplexer between the I/O pins, as well as the input buffers and associated internal circuitry.

The family also supports a range of I/O standards, including LVTTL and LVCMOS, both of which support 3.3-, 2.5-, 1.8-, and 1.5-V outputs. The input buffer thresholds can be programmed to support the same standards, regardless of the I/O bank voltage. Extended-range 3.3-V I/O current is also supported, which is far less common than the narrow-range version. All I/Os are 5-V tolerant for legacy connections. As for testability and in-system programmability, all of the devices support boundary scan via a JTAG IEEE 1149.1 interface that complies with the IEEE 1532 spec.

The CPLDs in the ispMACH 4000ZE family are available in packages ranging from 5 to 20 mm2 and with pin counts ranging from 48 to 144. Every device will be available in both thin quad flat-pack (TQFP) and chip-scale ball-grid array (csBGA) packages. The ultra-small csBGA footprint allows the devices to be crammed into tiny spaces often associated with portable/ handheld equipment.

The first two devices in the family include the 4032ZE and 4064ZE, which are both sampling now and support commercial and industrial temperature ratings. Projected pricing for the 4032ZE and 4064ZE is less than $0.70 and less than $0.85, respectively, both in 100,000-piece lots.

DANIEL HARRIS

LATTICE SEMICONDUCTOR CORP.
www.latticesemi.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish