Electronic Design

CPLDs Outshine HDLC Controllers In A Multichannel Design

Programmable Logic Handles Performance Needs While Offering Customization Not Available With Off-The-Shelf Controllers.

High-level data link control (HDLC) is one of the most enduring and fundamental standards in communications. With its roots in IBM's x.25 protocol, today it is found in a wide range of communications applications. These include leading-edge systems that use xDSL transport, frame relay, and ISDN. Because HDLC also forms the basis of Signaling System 7 (SS7), it's present in most of the worldwide telecommunications network, including cellular base stations.

A variety of HDLC controller chips are available from companies like Rockwell Semiconductor, PMC-Sierra, and Siemens. In addition, microprocessors from Motorola and AMD integrate HDLC controllers on-chip. All of these solutions strive to offer flexibility and high performance. This article describes a complex programmable-logic-device-based approach that fulfills high-performance requirements, while offering a degree of customization that's not available with off-the-shelf products.

HDLC fulfills Level 2 of the Open System Interconnect (OSI) model of communications. It includes an 8-bit begin-frame flag, a 16-bit address, an 8- or 16-bit control field, variable-length payload data, a 16- or 32-bit cyclic-redundancy-check (CRC) field, and an 8-bit end-of-frame flag. HDLC is specified in the ISO/IEC 3309 standard. It provides a convenient method of transporting packet information through a network, whether it's by x.25 transactions, Switch Virtual Circuits (SVCs) in frame relay, ISDN D-channel, call setup in a cellular base-station, or Internet Protocol (IP) on xDSL transport.

System Description
The HDLC controller consists of a pulse-code-modulation (PCM) highway for the full-duplex HDLC interface, memory controller/SDRAM buffer, and peripheral-components-interconnect (PCI) interface. The interface accepts 32 full-duplex HDLC frames from a PCM highway interface, which operates at 2.048 MHz. Each channel occupies one 8-bit timeslot on the PCM highway. The SDRAM frame buffer serves as the interface point between the PCM highway and the PCI bus. The configuration registers are also stored in SDRAM. Memory controller performs arbitration between PCI and HDLC accesses and DRAM refresh.

Receive HDLC frames are processed according to the HDLC protocol, and data octets are submitted to the memory controller to be written into the SDRAM frame buffer. Receive-buffer-full and end-of-frame events generate a PCI interrupt. The host on the PCI bus then reads the interrupt status register (ISR) to determine the source channel of the received frame data. The frame buffer stores frame status and error bits, along with the receive packet data.

From data deposited by the host CPU in the SDRAM frame buffer, the HDLC transmitter creates HDLC frames. Once a buffer has been transmitted, the HDLC controller signals an interrupt. The host CPU then writes more frame data into the transmit buffers.

Using as few CPLD macrocells as possible to implement the large number of HDLC and PCI registers is a major challenge. A brute force implementation of a 32-channel, HDLC state machine and PCI configuration register space could require as many as 5000 macrocells. Normally, one would consider using a high-register-count device beyond the largest CPLDs available in the market.

Because large frame buffers are required for host CPU efficiency, however, external memory is required. This memory can also be used to store PCI configuration and HDLC state-machine information. Taking advantage of the external memory, the HDLC controller is implemented using only one state machine and CRC generator. As each channel is processed, the state and CRC of the current channel is stored in the SDRAM frame buffer. The next channel's state and CRC information is re-stored from the SDRAM.

The design takes advantage of the time-division-multiplexing (TDM) nature of the PCM data, allowing the high-speed CPLD to reuse the state-machine logic for each channel. The high-speed CPLD is also used for arbitration logic between different functional blocks. This permits the design to be realized in significantly fewer macrocells.

PCM Interface
The HDLC interface consists of a PCM Transmit (PCMT), a PCM Receive (PCMR), a PCM Clock (PCMCLK), and a frame sync (PCMF) signal. PCMCLK operates at 2.048 MHz. The PCMT and PCMR signals are time-division multiplexed in a fashion commonly referred to as a PCM highway. There are 32 8-bit timeslots, numbered 0 to 31. Each timeslot repeats at a 125-µs interval. Timeslot 0 is denoted with the high-to-low transition of the PCMF signal. The PCMF signal will remain low for at least one timeslot.

Each timeslot contains one channel of HDLC traffic at 8 bits/125 µs, or 64 kbits/s. Timeslot 0 is assigned as HDLC channel 0. The rest of the timeslots are similarly assigned up to 31.

The HDLC frames that are multiplexed/demultiplexed onto the PCM highway consist of a start flag, address field, control field, variable-length data packet, frame-check sequence (FCS), and end flag. For this implementation, the address and control fields are decoded by the system software.

The flag byte (01111110) indicates both the start and the end of an HDLC frame. Zero stuffing/destuffing is performed on the HDLC packets whenever five contiguous 1 bits are transmitted/received.

Memory Map
The HDLC controller 1-Mbyte memory map is divided into two sections. Lower memory is used to store the PCI configuration, interrupt-service registers (ISRs), channel enable register, command register, databank register, status registers, buffer pointer/state registers, and CRC registers. These registers occupy the first 1536 bytes in memory. The remaining portion of lower memory, 0x00600 through 0x7FFFF, is available for other use. All these registers are located in system SDRAM, except for the interrupt service and command registers, which are mapped into the CPLD.

Upper memory, 0x80000 through 0xFFFFF, provides transmit and receive buffers for all 32 HDLC channels. Each transmit and receive channel has two 4-kbyte buffers. The buffer addresses are aligned so that the address decoding can be done directly from the state and status bits.

Transmit
After system initialization, the HDLC transmitter checks the command register and waits until transmission is enabled. The command register is set/reset by the system software. Once transmission is enabled, the channel enable register is examined to see if each channel is enabled for transmission. If the channel is disabled, the byte value stored in the databank register is transmitted during that timeslot.

Channels are processed sequentially and multiplexed onto the PCM highway. When the HDLC controller sees a channel enabled for transmission, it loads the channel's state, status, and CRC registers from memory. The state register is decoded to determine which channel buffer and status register are currently active. After each 8-bit timeslot is transmitted, the channel's state, status, and CRC registers are written back into the SDRAM memory.

Once the system CPU has written data into a transmit frame buffer, the CPU sets the Go and Done bits and the number of bytes to be transmitted in the transmit status register. The HDLC transmitter tests the Go bit as it prepares to transmit that channel's data. If a frame transmission is in progress and the Go bit is not set, the HDLC controller sends an end-of-frame delimiter. The controller then sets both the Abort bit in the channel status register and the appropriate bit in the ISR register, generating a PCI interrupt. The transmitter sends back-to-back start and stop flags until more data is available.

The HDLC frame buffers are used in "ping-pong" fashion with the HDLC transmitter—reading from one while the CPU writes to the other. The HDLC controller decodes the ping-pong bit in the channel state register to determine the active status register and channel buffer. Bit stuffing is performed as the channel frame data is read from the buffer. After every five consecutive ones, a zero is inserted. Once the last byte has been read from the buffer, the HDLC controller clears the Done bit in the channel status register and generates a PCI interrupt, indicating that the buffer is now available. The CPU indicates an end of frame by setting the EOF bit in the channel status register. When the HDLC detects the EOF, it transmits the FCS and end-of-frame delimiter. The FCS, a 32-bit CRC, is computed using a 32-bit, linear-feedback shift register.

Receive
After system initialization, the HDLC receiver checks the command register and waits until reception is enabled. The command register is set/reset by the system software. Once reception is enabled, the channel enable register is examined to see if each channel is enabled for reception. When the HDLC controller sees a channel enabled for reception, it loads the channel's state, status, and CRC registers from memory. The state register is decoded to determine which channel buffer and status register are currently active. After each 8-bit timeslot is received, the channel's state, status, and CRC registers are written back into the SDRAM memory.

The receiver demultiplexes the PCM highway and processes the channels sequentially. After a channel is enabled, the receiver waits for the start-of-frame (SOF) delimiter. Once SOF is detected, the receiver begins writing the channel data into the receive buffer. Bit unstuffing is performed on the incoming data stream, along with CRC calculation.

When the HDLC receiver has filled a frame buffer, it sets the Full bit in the channel status register. The receiver also toggles the ping-pong bit, indicating that the alternate frame buffer should be used. If the EOF delimiter is also detected, the EOF bit is set. A CRC and frame-length check is performed. If a CRC error is detected, the CRC bit is set as well. In addition, if the frame is either too long or too short, the long and short bits are set. If the transmission was error-free, the OK bit is set. A PCI interrupt is then generated, indicating that the buffer must be emptied.

Bus Arbiter/SDRAM Controller
The bus arbiter/SDRAM controller interfaces directly with the SDRAM. It generates the row-address-strobe (RAS) and column-address-strobe (CAS) signals during memory accesses, performs refresh cycles, and arbitrates between memory requests from the HDLC transmitter, receiver, and PCI host. Both the arbiter/controller and the SDRAM operate at the 33-MHz PCI bus speed.

All memory accesses are made through the SDRAM controller. Because the SDRAM supports burst mode, the arbiter/controller supports different types of bus requests to optimize available bus bandwidth. Status requests are given the highest priority during arbitration. Within a single HDLC timeslot, up to 17 possible memory accesses can occur. This includes the loading and storing of channel enable, state, status, and CRC registers, as well as frame data.

The PCM highway, 2.048-MHz data rate, however, is relatively slow compared to the 33-MHz PCI bus speed. Each HDLC timeslot is approximately 3096 ns. At the PCI bus speed, this translates to up to 103 possible memory accesses. By allowing the memory accesses to occur without any priority assigned, there could be more than 17 page faults for every HDLC timeslot. This would leave very little available time for the PCI host to load and unload the transmit/receive buffers.

By assigning the highest priority to status/state/CRC register requests, any page faults can be avoided while loading and storing these registers from memory. Memory requests are prioritized in the following order: status request, refresh, Rx/Tx request, and PCI request. Memory requests are made by asserting the appropriate request signals. If a request is accepted, the arbiter/controller grants the bus to the requester by asserting the appropriate bus grant signal. If a refresh cycle is in progress during a memory access, the arbiter/controller will insert wait states.

The PCI host, HDLC transmitter, and HDLC receiver all interface to the SDRAM using the same address, data, and write-enable buses. This is easily accomplished in a CPLD with internal tristate busses. For this design implementation, the address bus is 20-bits wide, the data bus is 32-bits wide, and the write enable bus is 1-bit wide.

PCI Interface
For a PCI interface, a CPLD must have PCI compatible I/Os, which permit the PCI bus to be driven directly. The CPLD must also have a sufficient number of macrocells to implement a PCI master interface, along with the HDLC transmitter/receiver and arbiter/SDRAM controller. A minimum of 47 signals must be supported to implement a PCI master.

The PCI specification requires the first 256 bytes of lower memory to be reserved for the PCI configuration space. All PCI-compliant devices must support the vendor ID, device ID, command status, revision ID class code, and header-type fields. The PCI controller initializes these PCI registers during power-on reset. To indicate that INT#A is enabled, the PCI interrupt-pin register is also initialized.

The ISRs are set by the HDLC controller during transmit/receive. They indicate whether the buffer is empty or full, or if a frame must be aborted during a transmission error or buffer time-out. The outputs of all the ISRs are OR'd together and drive the PCI Int#A pin. The PCI host responds to interrupts by checking the ISRs and servicing the appropriate channel. After the channel interrupt has been serviced, the PCI host clears the appropriate bit in the ISR.

CPLD Logic Utilization
The CPLD macrocell-utilization requirement can be divided into three parts: HDLC transmit/receive, arbiter/SDRAM controller, and PCI master interface.

A large percentage of the macrocell utilization for the HDLC controller is devoted to the Channel Enable, status, state, CRC, and ISR registers. The number of macrocells used in the transmit and receive state machines is small in comparison. It is not practical to implement a different set of these registers for each channel, nor is it necessary. Because the PCM highway data rate is relatively slow, and the channels are processed sequentially, the same set of transmit/receive registers can be used for each channel. Approximately 300 macrocells are used for the HDLC controller implementation. The arbiter/SDRAM controller takes up approximately 128 macrocells, which includes 20-bit memory-decode logic and a refresh state machine, as well as tristate bus arbitration. The PCI master interface can be implemented in approximately 128 macrocells. This includes the minimum signals needed for a PCI master and the initialization of the registers in the PCI configuration space. A total of 556 macrocells are required for the CPLD implementation.

The I/O utilization is minimal, due largely to the implementation of address and data buses with the CPLD's internal tristate busses. The PCI master interface requires 47 I/Os, plus one for the Int#A to interface to the PCI bus. For the HDLC interface, the HDLC transmitter/receiver requires four I/Os. Finally, the SDRAM controller requires 47 I/Os to interface to the SDRAM. This includes the 32-bit SDRAM data bus. In total, 99 I/O cells are needed in the CPLD.

The implementation example is shown in the Lattice ispLSI8840. There are a total of 840 macrocells and 312 I/O cells with register capability. The PCI drive capability and the 108-bit-wide tristate bus feature of the ispLSI8840 is used for the HDLC controller implementation.

For this given implementation, approximately 66% of the macrocells (556/840) and 32% of the I/O pins (99/312) on the ispLSI8840 are used. This leaves room for customization and additional logic implementation for the system. In-system programmability (ISP) of the CPLD makes the modifications and customizations—such as reconfiguring the buffer sizes by manipulating the SDRAM configuration, the arbitration priorities, and the HDLC timeslots—as easy as rewriting software via the VHDL code. The hardware reconfiguration is handled by simply downloading the new fusemap through the four- or five-wire standard JTAG interface. The JTAG port also provides access to the on-chip boundary-scan test registers.

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