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ASICs Take On More Of The System

As more logic and memory are integrated onto ASICs, manufacturers and foundries are shifting from 130- to 90-nm design rules. The smaller transistors possible at 90 nm enable a near-fourfold increase in gate capacities, permitting designers to pack about 40 million gates on a chip of about 25 mm on a side.

Yet few design teams can craft circuits with that complexity from gate-level building blocks. Design time would be excessive, and the chance for errors would rise dramatically. Advances in design tools, circuit synthesis, and compilation technology, coupled with the use of standard cell libraries and large blocks of reusable intellectual property (IP), have overcome most drawbacks to designing complex ASICs.

The basic ASIC design flow remains almost unchanged over the last half-decade or so. What has changed is the use of large blocks of IP and the increased cost of fabricating the masks needed to produce the chips. In the realm of IP, designers can already select from a wide range of rather complex functions, which just a few years ago were standalone chips themselves. Blocks of memory are perhaps the most popular of IP options, with many IP suppliers offering both fixed-size and compilable blocks of SRAM, flash, and DRAM.

Each memory block has its own challenges when integrated as part of an ASIC. With SRAM, density and leakage currents could be key when more and more bits are needed. Arrays of a megabit and larger are perhaps better implemented with cells based on the much more area-efficient single-transistor DRAM storage elements, which can be made to look static with some additional logic. The technique, pioneered by Mosys, saves a considerable amount of chip area when large arrays are required. It also reduces the leakage current versus a large array based on static memory cells. At this point, process complexities still limit the use of embedded flash memory and embedded DRAM. Both memory types require additional process steps to add the memory to the process flow. That, in turn, increases the ASIC's cost.

Though it's not the only cost factor when going the custom-chip route, the cost of the mask set to fabricate a design based on 90-nm process rules will exceed $1 million. Projections for the next process point of 65 nm show a mask cost between $1.5 million and $2 million.

Gaining popularity due to the lower mask costs is the "structured array," or "platform" chip. These two names refer to a quick time-to-market ASIC solution that still provides most ASIC features, but with a mask cost equaling only half to a third of a full ASIC. Suppliers and analysts argue about what features qualify a chip as a structured array versus what qualifies as a platform solution. In general, both use premanufactured silicon with various resources pre-integrated in the silicon (memory, high-speed I/O interfaces, phase-locked loops, and an array of uncommitted gates). Structured arrays tend to be more generic and not targeted to any application niche, while platform solutions (like LSI Logic's RapidChip family) also come with a prequalified collection of soft IP blocks that fit a particular market application segment, such as networking.

The platform and structured ASIC offerings from suppliers, including AMI, LSI Logic, NEC, and Toshiba, arm designers with a solution that delivers near-ASIC integration levels. At the same time, they also offer a shorter turnaround time and a lower nonrecurring engineering charge because only two to four mask layers need to be created. Design-verification costs and times are also reduced because much of the pre-integrated IP is already verified and prequalified.

Other companies feel their products also fit this market space. PalmChip offers several platform chips based around an ARM core and pre-integrated resources targeted at storage control and other markets. FPGA supplier Altera believes its HardCopy mask-programmed FPGA replacement actually fits the definition of a structured array. Some complex FPGAs could also qualify as platform or structured ASIC solutions, as they have many pre-integrated resources—PLLs, high-speed serial I/Os, blocks of memory, processor cores, and so forth.

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TOP TEN

  • BY MID-2004, THERE WILL BE widespread availability of 90-nm process technology from most of the ASIC suppliers. This process node will allow designers to integrate about 40 million gates on a single chip.
  • EXPECT FPGA SUPPLIERS to deliver the first samples of chips with as many as 10 million ASIC equivalent gates. These FPGAs will also be based on new 90-nm processes available from foundries such as TSMC.
  • CONTINUED GROWTH OF ON-CHIP MEMORY will push more designers to use an SRAM replacement based on a DRAM core. Dubbed the 1T-SRAM by Mosys, the memory array can replace most large SRAMs in applications that don't demand the shortest access times. The array is much more area-efficient than static RAM blocks and often features lower standby currents than SRAM leakage currents, suiting the 1T arrays for low-power/portable systems.
  • HIGH-SPEED SERIAL INTERFACES, both low-voltage differential logic and serializer/deserializers (SERDES), will continue as popular resources ASIC suppliers pre-integrate into various structured and platform ASICs. They'll also be included as IP building blocks as part of the design libraries.
  • THE PACE OF PROCESS DEVELOPMENT will go undaunted as ASIC suppliers develop design rules for 65-nm processes. Although no products will probably appear until late 2005, design rules will be firmed up by late 2004 or early 2005 to update IP libraries.
  • ASIC SUPPLIERS WILL ROLL OUT a wide range of structured ASICs and platform chips. These will provide designers with an alternative to the high mask costs associated with a full ASIC design. Leading the pack is LSI Logic with its RapidChip platform family, but companies such as NEC, Toshiba, and others will be releasing 2G structured ASIC solutions that pack more resources and flexibility than 1G versions.
  • MORE EXTENSIVE USE OF FLIP-CHIP PACKAGING will provide higher pin counts and reduce the signal path's delays going from the chip to the package and from the package to the circuit board. As chip performance increases, the package becomes one of the limiting factors in overall system performance. As a result, companies must focus more on packaging issues.
  • USE OF SERIAL INTERFACES will also skyrocket over the next year. SERDES-based interfaces will allow designers to replace wide parallel buses with more noise-immune serial channels, thus helping to counter the trends toward ever higher pin counts. The serial interfaces can also aid in reducing overall chip power, a major concern with increasing gate counts and operating speeds.
  • MASK COSTS WILL ESCALATE past the $1 million mark. In fact, estimates are already pegging the cost for a 65-nm design mask set to be somewhere in the $1.5 million to $2 million range. Those cost levels may limit the number of companies that can afford to do a full ASIC design and possibly push toward structured ASICs or platform solutions.
  • AS DESIGN RULES SHRINK to 90 nm, it will be easier for ASIC suppliers to produce full-CMOS mixed-signal circuits that implement full RF transceiver functions that operate at 2.4 and even 5 GHz. This will potentially eliminate the need to use silicon-germanium processes and thus allow full single-chip integration at a lower cost point.
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