Electronic Design

Digital ICs> Structured ASICs: Balm For An Ailing ASIC Market

It seems that just about every day we read another prediction about the ASIC market's demise. One prognosticator says it's the decline in ASIC design starts. Another feels it's the difficulties in designing a complex systems-on-a-chip (SoC). It could be the rising nonrecurring engineering (NRE) costs. Maybe it's the increase in unit volume necessary to justify manufacturing an ASIC with 90-nm design rules. Whatever the reasons, the ASIC market is under assault on several axes simultaneously.

Over the last 12 to 18 months, a new category of ASIC has arisen, and it potentially holds the answer to many of these issues. The creation of the structured ASIC (SA) is welcome news to an ASIC market that has seen many of its traditional strengths called into question when compared to standard, off-the-shelf products. Because the SA combines the strengths of the gate array (GA) and the standard cell (SC), the SA could pump new life into a market that's clearly ailing.

The main attributes of the SA are its low NRE costs, relatively quick turnaround times, and good performance and density over GAs and SCs. In addition, it fits squarely between field-programmable gate arrays (FPGAs) and SCs in terms of its total cost/volume proposition. Furthermore, the SA's performance places it above FPGAs and within reach of SCs. This is important for those designers who can't justify launching a lengthy design effort using SC or SoC methodologies yet need more performance than that offered by either GAs or FPGAs. Their main need is a product with enough flexibility to allow differentiation from their competition regarding their system solution.

This brings up an interesting question: Will the advent of the SA bring new business opportunities and revenues to the ASIC market? The answer is a qualified yes! The qualifier in this case depends on where the new business opportunities come from. Semico Research Corp. believes the structured ASICs will pull revenue from five different areas: GAs, SCs, SoCs, FPGAs, and standard products. In the case of the first four categories, SAs merely switch the revenue from one area to another, as these revenues already come from ASIC designs and will remain in the ASIC market. New business opportunities for the ASIC market are represented by the conversion of standard product solutions to the use of SAs.

This last grouping consists of customers who are undecided about what direction to take in crafting their silicon solutions. They need more performance than what's available from GAs, but they either can't wait for or can't afford an SC or SoC design. In this case, FPGAs are too expensive to fit into the bill of materials. For this group of users, SAs represent the perfect alternative. There is the possibility to have a highly differentiated solution without a crushing NRE charge and in a reasonable design time window.

While SAs aren't the total answer in terms of returning the ASIC market to its last revenue peak, SAs do represent a re-invigoration of the market. Semico believes ASIC market revenues will reach about $2.0 billion by 2008, and enough suppliers will enter the market with different types of solutions to reach critical mass among potential users.

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