Electronic Design

DRAM Enhancements Accelerate Servers, Routers, and Other Systems

Two high-speed DRAM technologies developed by Elpida boost the performance of servers, network routers, PCs, and other IT infrastructure systems. Developed in cooperation with Hitachi Ltd., the first technology speeds route-finding in network routers and cache memory applications in servers. It incorporates high-speed memory arrays that use two memory cells per bit (dubbed a "twin-cell memory"), and a high-speed three-stage data sensing scheme.

The twin-cell memory uses the same memory cells as general-purpose DRAMs. But two cells per bit eliminate imbalances and noise, enabling high-speed random access. To better sense the data, an ultra-high-sensitivity main amplifier was configured in three stages. This avoided the need for a separate sense amplifier.

A prototype chip packing 144 Mbits was fabricated and evaluated using Elpida's 110-nm DRAM process for general-purpose DRAM production. The chip achieved exceptional performance with random access time comparable to fast SRAMs.

The second new technology is a circuit approach for 1-Gbit DRAMs that supports DDR1 and DDR2 on one chip. This would let Elpida manufacture a single chip for both markets and deliver more of the memory type in higher demand.

Taking advantage of the regularity of the external input commands of DDR2 DRAMs, the scheme results in an input logic circuit that does not require an excessive timing margin. This was done by employing input latches that have an internal clock frequency of twice the DDR2's input clock. Designers were then able to create two internal clock systems differentiated by their phase, which differs by one external clock cycle. Also, commands issued by either clock can be captured. A circuit results that has sufficient operating margin for the DDR2 clock with the smallest period (2.5 ns) but with the same circuit configuration as the input latch block of DDR1.

Test and evaluation of a 1-Gbit DRAM fabricated on a 100-nm process proved that a 215-ns clock cycle can be realized, even under worst-case external power-supply conditions. Speeds of 400 Mbits/s for DDR1 and 800 Mbits/s for DDR2 can be achieved, while chip area increased by only 0.3%.

Elpida presented technical papers on the two technologies at the 2004 Symposium on VLSI Circuits, held in Honolulu June 17-19, 2004.

Elpida Memory Inc.
www.elpida.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish