Electronic Design

Electronic Design UPDATE: February 15, 2006


Electronic Design UPDATE e-Newsletter Electronic Design Magazine Electronic Design ==> www.electronicdesign.com February 15, 2006


*************************ADVERTISEMENT************************** Improve your knowledge of time-frequency analysis, time-series analysis and wavelets The National Instruments Advanced Signal Processing Toolkit is a suite of easy-to-use, palette-based tools, example programs and utilities that extends the LabVIEW graphical development environment with cutting-edge measurement-oriented signal processing and analysis. Engineers and scientists now can access new graphical tools for simplifying work that incorporates time-series analysis, time-frequency analysis and wavelets. http://news.electronicdesign.com/t?ctl=20D1C:484C79 **************************************************************** Today's Table Of Contents: 1. News Focus *Measurement Technology Accurately Calculates On-Chip Jitter 2. News From The Editors *CMOS Image Sensor Focuses On Camera Phones *Lithography Method Shrinks IC Geometry To 26 nm *Multifunction Power-Management IC Benefits Portable Devices 3. TechView Scope *Automotive Fuel-Cell System Increases Cabin Space, Improves Performance 4. Upcoming Industry Events *RFID World *APEC 2006 *PCB Design Conference West 5. Book Review *"HDL Programming Fundamentals: VHDL and Verilog" Electronic Design UPDATE edited by Lisa Maliniak, eMedia Editor mailto:[email protected] **************************************************************** ********************** 1. News Focus ********************** Measurement Technology Accurately Calculates On-Chip Jitter At last week's IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, NEC unveiled technology that achieves what the company claims is the world's most accurate on-chip measurement of clock signal quality (jitter). Research into this technology was undertaken to support the design and development of new LSI chips, as well as improve their performance and reliability. NEC and NEC Electronics embedded a circuit within an LSI chip to measure its signal deterioration. As a result, they have developed a new LSI design scheme to permit further performance enhancements as well as actual data observation in the field. By using this design scheme, it will be possible to gather and analyze the amount of signal-quality deterioration inside an LSI chip when it is being used in a system, even while the device is running a program. The new technology improves measurement accuracy by one full decimal place over existing methods, allowing for a 1-ps measurement of clock fluctuation. It not only observes clock-signal fluctuation in real time, it also can output that data as a digital signal. Normally, jitter only can be measured once per oscillation period. By copying the clock signal, NEC and NEC Electronics carried out multiple measurements during a single clock cycle's oscillation period. Instead of simply copying the clock signal, the copied clock signals were designed to carry equally distributed information about the time fluctuation to produce highly accurate results. NEC Electronics ==> http://news.electronicdesign.com/t?ctl=20D1D:484C79 **************************************************************** **************************************************************** Electronic Design Is Looking For A Technology Editor Are you a talented engineer with a knack for writing? Then we may have the job for you. Electronic Design is looking for a new Technology Editor to do front-line writing for print and associated eMedia properties. This editor will develop and write feature reports, product coverage, news, and columns. The qualified candidate needs the ability to clearly present technical information in written form. A strong electronic engineering background and familiarity with any of a wide range of electronic technologies is required, and expertise in digital semiconductor technology is preferred. Interested candidates should e-mail their resume to Editor-in-Chief Mark David at mailto:[email protected] **************************************************************** *******************Live on ElectronicDesign.com*********************** Free Webcast: Boost DSP Throughput with Low-Cost FPGAs Wednesday, February 22, 2006 at 2:00 pm ET Designers are increasingly turning to FPGAs to help accelerate DSP performance and add extra compute power as a coprocessor. Lattice Semiconductor's latest-generation FPGAs have built-in, advanced DSP blocks that each contain a pipelined multiplier-accumulator engine. Learn how to implement DSP functions in these latest low-cost, high-performance FPGAs. One lucky participant will receive the ispLEVER Development Tool for FPGA and CPLD design. Register today! http://news.electronicdesign.com/t?ctl=2012B:484C79 ********************************************************************** ********************** 2. News -- From The Editors ********************** ***CMOS Image Sensor Focuses On Camera Phones Kodak's KAC-01301 1.3-Mpixel CMOS image sensor is specifically optimized to enable cost-effective designs in next-generation mobile phones. The KAC-01301 sensor provides the image quality currently available from CCD image sensors while taking advantage of the power, integration, and cost benefits traditionally associated with CMOS technology. It leverages the company's Pixelux technology, an architecture that uses pinned photodiodes with low dark current and a four-transistor shared-pixel structure. The shared-pixel architecture also allows for charge-domain binning of multiple pixels on the imaging array, enabling operating modes with increased sensitivity for low-light image and video capture. The KAC-01301 image sensor is expected to sample in the second quarter of 2006. Eastman Kodak Company ==> http://news.electronicdesign.com/t?ctl=20D1E:484C79 ***Lithography Method Shrinks IC Geometry To 26 nm A new IC lithography method under development at the Rochester Institute of Technology has led to imaging capabilities beyond that previously thought possible. Professor Bruce Smith and a team of engineering students developed a method known as evanescent wave lithography (EWL), which can optically image what may be the world's smallest semiconductor device geometry. The imaging technology created geometries down to 26 nm, a size previously possible only via extreme ultraviolet wavelength. Using the International Technology Roadmap for Semiconductors as a guide, the development comes at least five years sooner than anticipated. Knowledge gained from EWL will facilitate the development of microelectronics and nanotechnology that will fuel a good deal of product development over the next five to 10 years. Smith will present his research at Microlithography 2006, a symposium sponsored by the International Society for Optical Engineering, on February 21 in San Jose, Calif. Rochester Institute of Technology ==> http://news.electronicdesign.com/t?ctl=20D1F:484C79 ***Multifunction Power-Management IC Benefits Portable Devices By integrating a slew of functions on a single chip, the STw4810 power-management IC saves money and board space over previous solutions that used multiple chips and components. In addition to multiple dc-dc converters and programmable regulators, the STw4810 integrates a complete USB-OTG (USB On-The-Go) transceiver and a memory-card interface. It also offers processor-supply monitoring and reset control. The STw4810 is designed as a partner for any multimedia application processor engine (APE) used in portable products such as mobile phones and PDAs. The part comes packaged in a 4.6- by 4.6-mm VFBGA or 6- by 6-mm TFBGA package. Volume production is planned for late in the first quarter of 2006. Pricing is set at $3.00 each in 1000-piece quantities. STMicroelectronics ==> http://news.electronicdesign.com/t?ctl=20D20:484C79 **************************************************************** ********************** 3. TechView Scope ********************** Automotive Fuel-Cell System Increases Cabin Space, Improves Performance The mainstream fuel-cell automobile is one step closer to a showroom near you. Honda will begin producing its next-generation FCX Concept hydrogen-powered fuel-cell vehicle (FCV) in the next three to four years. Its fuel-cell system uses a unique low-floor fuel-cell platform to deliver more power in less space. Oxygen and hydrogen flow from the top to the bottom of Honda's V Flow fuel-cell stack for a vertical gas flow. The fuel cells are arranged vertically in the center for high-efficiency packaging. This compact layout puts out 100 kW while saving space, producing the full-sized passenger cabin that other FCVs lack. Water management is key to the FCX's fuel-cell performance. Cold-weather startup problems have been an obstacle in FCV commercialization. But the FCX's system uses gravity to efficiently discharge water formed during electricity generation. As a result, the FCX's startup performance matches the performance of typical gasoline engines in subzero temperatures. An efficient 80-kW motor sits at the front of the drive train. There's a 25-kW space-efficient motor at each rear wheel as well, further improving cabin space. A newly developed absorption material in the tank doubles capacity to 5 kg of hydrogen at 5000 psi, extending cruising range comparable to gasoline engines at 350 miles. In addition to the energy innovations, the car's sensors and intelligent cameras can recognize the driver and unlock the doors. The unit then sets the steering wheel, accelerator pedal, and instrument panel to the driver's preferred positions. It also senses the driver's line of sight and operates switches accordingly for hands-free operation of audio, air conditioning, and other systems. Honda ==> http://news.electronicdesign.com/t?ctl=20D21:484C79 *************************ADVERTISEMENT************************** Register Now for the Embedded Systems Conference Silicon Valley 2006! April 3-7, 2006 McEnery Convention Center, San Jose, Calif. 13 tutorials, 132 classes, 6 design seminars. Vital topics such as real-time development, hardware/software integration, debugging, programmable logic design, wired connectivity and security and more! Register by March 7th and save up to $200, use code UX3. http://news.electronicdesign.com/t?ctl=20D22:484C79 **************************************************************** ********************** 4. Upcoming Industry Events ********************** February 27-March 1, RFID World 2006 Dallas, Texas http://news.electronicdesign.com/t?ctl=1F7E5:484C79 March 19-23, APEC 2006 Dallas, Texas http://news.electronicdesign.com/t?ctl=20D23:484C79 March 26-31, PCB Design Conference West Santa Clara, Calif. http://news.electronicdesign.com/t?ctl=1CFBE:484C79 **************************************************************** ********************** 5. Book Review ********************** "HDL Programming Fundamentals: VHDL and Verilog" By Nazeih M. Botros For those who are new to hardware description languages (HDLs) or looking to refresh dormant skills, Nazeih Botros's "HDL Programming Fundamentals" provides a basic course in both VHDL and Verilog. There's a slew of books out there that take up either one language or the other. This book is a bit unusual in that it covers both in parallel. So it can be used to learn either language or both, as the reader deems necessary... Read the full book review at http://news.electronicdesign.com/t?ctl=20D24:484C79 **************************************************************** EiED Online -- Bus and Board Show: Part 2 Embedded in Electronic Design (EiED) Online is your source for technical insight and hands-on reviews. Read Technology Editor Bill Wong's latest EiED Online column, "Bus and Board Show: Part 2." This year's Bus and Board show brought out a range of issues, from the European Union's Restrictions on Hazardous Substances to VME's 25th anniversary. Hear about the new Aurora fabric, and find out what else Bill Wong discovered at the show. http://news.electronicdesign.com/t?ctl=20D25:484C79 ********************** TAKE A POLL! In his recent State of the Union Address, President Bush proposed an American Competitiveness Initiative. Which element of that initiative will best prepare the U.S. to compete in the global marketplace? -- Increased funding for technology research programs -- A permanent R&D tax credit -- More rigorous math/science education programs Vote at Electronic Design ==> http://news.electronicdesign.com/t?ctl=15410:484C79 ****************************************************************




Editorial: Mark David, Editor-in-Chief mailto:[email protected] Advertising/Sponsorship Opportunities: Bill Baumann, Publisher: mailto:[email protected]

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