Two new sequential flow-control managers combine the critical functions required to manage sequential streams of high-speed data—high-speed buffering, switching, domain transitions, multiplexing/demultiplexing, and random/sequential access. As a result, they eliminate much of the homegrown logic usually required to perform such operations.
The 72T6480 manager runs at 133 MHz and supports 48-bit wide data using up to 1 Gbit of external double-data-rate SDRAM. The 72T6360 version runs slightly faster at 166 MHz and uses a narrower 36-bit data word.
Both chips have independent read and write ports with associated read and write clocks that operate asynchronously at up to 166 MHz with a 6-Gbit/s throughput. The chips' bus-matching feature allows the inputs and outputs to be configured in an X36, X18, or X9 bus width ('6380) or X48, X24, or X12 ('6480). User-selectable error detection and correction can detect and correct single-bit errors when reading data from the external SDRAM.
The controllers can support SDRAM densities of 128 or 256 Mbits for a single device. Up to four devices can be connected to the flow controller. To meet the needs of systems that require more than 1 Gbit of buffering, the controllers can be configured in a depth-expansion mode so multiple controllers can be cascaded to hit multigigabit densities.
Both flow-control managers come in 324-contact plastic BGA packages. In 10,000-unit quantities, they cost $35 apiece. They use a 2.5-V supply for the core logic and either a 2.5- or 3.3-V supply for the I/O pins.
Integrated Device Technology