Electronic Design

Full-Throttle PowerQUICC Engine Revs Up Communication Systems

Sporting a souped-up communications engine and control processor, the latest PowerQUICC II communications processor—Freescale Semiconductor's MPC8360E—delivers nearly four times the performance of previous-generation PowerQUICC II devices.

The engine's dual custom RISC processors manage all the functions in the communications processor module (CPM). In turn, the CPM manages the packet throughput, interworking capabilities (without CPU intervention), multiprotocol support, and high channel density.

As a result, the MPC8360E delivers a combined full-duplex data throughput of up to 1.2 Gbits/s. It also supports over 2000 voice channels in Voice over Internet Protocol applications. With the chip, it's even possible to develop IP digital-subscriber-loop access modules (DSLAMs) that support up to 256 subscribers.

The enhanced 32-bit e300 PowerPC processor core that runs the applications, as well as the revamped dual 32-bit RISC engines that run the CPM, can run at clock speeds of 500 MHz. Clock speeds reach up to 667 MHz when process scaling permits the increased speed. The e300 CPU packs 32-kbyte instruction and data caches (eight-way), as well as a superscalar architecture that runs up to three instructions per clock cycle.

The chip can leverage all of the software written for previous PowerQUICC family members. A security engine, added to improve encryption and decryption speed, runs DES, 3DES, MD-5, SHA-1, AES, and ARC-4 algorithms. Also, the engine includes a public key accelerator and a random-number generator.

Eight unified communications controllers (UCCs) in the CPM support virtually any interface. The UCCs can be configured as up to eight 10/100-Mbit/s or two 10/100/1000-Mbit/s Ethernet ports. The CPM also packs two Utopia/PSO physical-layer (PHY) level 2 ports with up to 124 logical PHYs to support ATM or packet data for Sonet/SDH, xDSL, or other networks. In addition, the UCCs will support integrated multichannel time-division multiplexing (TDM)—up to two serial interfaces that provide a maximum of 64 logical channels.

A multichannel communications controller included in the CPM is dedicated to TDM. It can support eight serial interfaces for up to 256 logical channels.

Other interfaces include a double-data-rate (DDR) memory controller. It provides a 32- or 64-bit single memory port or dual 32-bit memory port that operates at 266 or 333 MHz. A 66-MHz PCI 2.2 interface with a DMA controller offers both Host and Agent mode support. Dual UARTs, a pair of I2C ports, an interrupt controller, several timers, and some general-purpose I/O lines also are available. Freescale's CodeWarrior development tools support the chips, as do multiple third-party tools and application libraries.

The MPC8360E and the cost-reduced 8358E will be available in sample quantities in the third quarter. The 8358E only runs at up to 400 MHz. It has a single 32-bit DDR interface and fewer Ethernet, Utopia, and HDLC channels. In lots of 10,000, the MPC8358E will cost $34.43, while the 8360E will go for $44.39.

Freescale Semiconductor Inc.
www.freescale.com

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TAGS: Freescale
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