As desktop platforms migrate to Gigabit Ethernet to improve the data bandwidth, servers and network backbones must move to 10 Gbits/s to avoid bottlenecks that disrupt data flow. However, 10-Gbit Ethernet switches have been pretty expensive, typically costing about $20,000 per port in a 12-port system. That puts them out of reach for many small- to medium-sized organizations.
To that end, Fujitsu grabbed the opportunity to develop a significantly lower-cost solution for wire-speed layer 2 functions in high-performance server designs, blade servers, and switches. The company devised the first Ethernet switch fabric on one chip that incorporates a full dozen 10-Gbit/s Ethernet ports. The chip can potentially reduce the per port cost to about $200—a drop of two orders of magnitude.
Along with the 12 ports, the MB7Q-3050BYL includes the high-speed buffer memories, the high-speed I/O macrocells, and a high-performance multiported memory that handles simultaneous read and write operations to and from all 12 10-Gbit/s ports. With all ports active, the chip has an aggregated bandwidth of 240 Gbits/s.
Each 10-Gbit/s port consists of a XAUI serializer/deserializer, providing four 2.5-Gbit/s bidirectional channels, and a 10-Gbit/s Ethernet media-access controller (MAC) that complies with the IEEE 802.3ae full-duplex standard using the Pause flow-control. All ports feed into a multiport memory subsystem that meets the throughput requirements, even with minimum-size Ethernet packets. Low latency is another feature of the memory subsystem: Pin-to-pin switching latency is only 450 ns. Previous systems often had latencies of several microseconds.
Combining all those elements enables the switch chip to satisfy the short-latency and high-throughput packet-switching requirements of high-end servers and advanced storage systems. The chip also provides efficient multicast support and reduced fall-through latency. On top of that, high-performance clustering is supported. The circuit allows cut-through routing, includes jumbo frame support, maintains four priority queues, and supports system expansion to scale the number of ports.
For layer 2 switching, the chip handles L2 unicast forwarding, address learning and aging, and multicast forwarding. Included on the switch circuit are lookup tables with 8k MAC addresses. Virtual local-area networks (VLANs) can be implemented on the fabric thanks to support for the 802.1Q VLAN multiple spanning tree standard and a VLAN table that handles up to 4k VLAN addresses. For bandwidth sharing, the fabric implements a deficit round-robin algorithm. To support maintenance and value-added services, multiple statistics counters were incorporated to handle RMON and SNMP statistics collection.
Fabricated with 0.11-µm design rules, the Ethernet switch-fabric chip typically consumes about 15 W. To handle the 12 XAUI ports and the host interface, the chip comes in a 728-contact flip-chip BGA package that measures 35 mm on a side. In comparison, a 12-port Ethernet switch built with lower-integration devices might require about 20 times more space than the switch chip (610 by 430 by 710 mm) and consume about 60 times the power (about 2400 W) versus about 37 W (complete switch power rather than just the 15 W for the chip by itself).
A development board containing the switch-fabric chip and standard management information base support, device management support, and hardware diagnostics has been developed and is available for performance evaluation. Samples of the MB7Q3050BYL are immediately available and cost $750 each in lots of 10,000 units.
FUJITSU MICROELECTRONICS AMERICA INC.