Electronic Design
How Deeply Depleted Channel Transistors Work

How Deeply Depleted Channel Transistors Work

SuVolta has revealed a bit more about their Deeply Depleted Channel (DDC) low power, CMOS transistor technology designed for embedded SoCs (System-on-chip). SuVolta's PowerShrink transistor (see DDC Transistor Brings Low Power And High Performance To Portable Devices) uses an improved planar bulk CMOS technology that can be built use existing CMOS fabs. The process flow modifies only 5% of the normal planar bulk CMOS design flow. It is working at 65nm and 28nm and the approach scales below 20nm.

DDC competes with 3D and Full Deplete-SOI (FD-SOI) technologies (Fig. 1). Intel is using 3D FinFET transistors in its new processors (see Moore's Law Continues With 22nm 3D Transistors) and it requires more process changes. It also targets high performance, multicore processors. FD-SOI has some heavy hitters behind it including a consortium that includes STMicroelectronics, IBM, ARM and Globalfoundaries. It also simpler process than FinFET.

SuVolta's approach is designed to reduce leakage and active power consumption. It does this by paying close attention to threshold voltage (VT) variation and carrier mobility. Reduce the VT variation and all the transistors can operate at the same speed. Essentially SuVolta changes the regular planar bulk CMOS process so the usual, single CMOS channel layer into three layers (Fig. 2).

  • Top layer: Undoped or very lightly doped region
  • Middle layer: VT setting offset region
  • Bottom layer: screening region

The top layer removes dopants providing a deeply depleted channel. It reduces random dopant fluctuation (RDF) that in turn allows VDD scaling. This enhances mobility and increases the effective current the channel can handle.

Middle layer is called the VT setting offset region. It is designed to set the transistor threshold voltage levels without degrading channel mobility. The layer also improves sigma VT compared to conventional CMOS transistors.

Bottom layer, of screening region, filters the charge in the channel and controls the depletion layer depth. It is the base for dynamic VT adjustment that can be done by biasing. This is optional and up to the SoC designer.

The DDC transistor cuts power requirements by 50% while reducing operating voltage (VDD) by up to 30%. It does this using dynamic adaptive body biasing. It can be more effective at threshold voltage management compared to the usual fixed body bias design.

Overall, the design approach can deliver more than a 10% increase in drive current (IEFF) by increasing channel mobility by 30% or more. SuVolta's technology allows designers to correct systematic manufacturing variations. This improves overall yield and decreasing VT variation up to 50%.

TAGS: Intel
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