As consumers continue to demand increased functionality in their digital devices, designers are challenged to look beyond performance and power considerations to build new levels of security into their systems-on-a-chip (SoCs) to ensure the integrity of devices and their content.
System designers need to consider the many digital rights management (DRM) specifications as well as how to architect a secure subsystem that protects and manages the “secret key” that lets the device decrypt and access high-definition content streams. Considerations also extend to the access of high-speed ports, such as an IEEE 1394 port that needs to be disabled during high-definition movie decryption. Disabling the port prevents the unauthorized downloading of protected high-definition content.
Secure system designs require a chipwide approach. Any system is only as secure as its weakest element, and retro-fitting security solutions to a system that has not been designed with security in mind is only a temporary fix. In addition to understanding the basic requirements of a secure SoC, the protection of a device’s “secret key” and content is vital in a system designer’s ability to provide leading-edge products.
Looking to the future, a new generation of standards is enabling a wide range of secure peripherals with individualized access levels, avoiding the problems that can occur with a single trusted environment. If one peripheral is breached, it can be used to access all the others. With multiple levels of access, the peripherals and assets that need to be most secure, such as those handling certificates and credit card numbers, can still be kept secure from other peripherals.
The Open Core Protocol International Partnership (OCP-IP) specification is defining a standard way of building secure peripherals based on a signal on the bus that can be defined by an arbitrary number of bits to set different levels of access.
This is different from recent moves to create standard specifications to provide secure communication links between separate devices in a system. These largely target conditional access systems and protecting the content in pay TV systems.
So far, trusted environments have been built with proprietary technology as closed systems and only on new processor cores. As a result, new applications are time-consuming to develop and verify. Also, they aren’t backward-compatible. There are better ways forward. Coming from the server market, the MIPS architecture has been designed from the beginning to be secure.
The MIPS32 4KSd core augments the 4KEc embedded core with a secure MMU that scrambles the cache interface and adds cryptographic acceleration through the SmartMIPS instruction extensions as well as anti-analysis features. This mix of hardware and software adds less than 10% to the size of the core but provides a secure system that has already been used in smart cards as well as smart-card readers/terminals. This approach also suits many other trusted systems and applications related to payment, access, and healthcare where the authentication of an individual’s identity is important.
The SmartMIPS Application Specific Extensions are extra instructions for the MIPS32 architecture optimized to help cryptography and secure applications. They were jointly defined with smart-card supplier Gemplus (now Gemalto) to combine cryptography enhancements, secure memory spaces, code compression, and virtual-machine performance enhancements. Among other applications, the SmartMIPS ASE enables an inexpensive, low-power, and complete smart-card processor solution.
The cryptography enhancements speed public-key data security algorithms, providing three to 10 times the speed of a software-only implementation. Secret-key operations also gain, but to a lesser extent.
Software cryptography allows easy field upgrades of cryptography algorithms. Therefore, a potential breach in the security algorithm doesn’t require a recall of the actual cards. Also, the accelerated software cryptography enables the choice of algorithm (such as RSA, DES, AES, and elliptic curve cryptography—ECC) on a per-application basis.
The Secure Memory Spaces protect sensitive consumer data by application, preventing unauthorized data access by rogue applications. Built-in code-compression minimizes memory use, preserving scarce memory resources.
As the core is synthesizable and has a high maximum frequency, the SoC designer has many options in floor planning. This is important, as some analysis can determine the activity patterns of particular execution units and deduce some of the code activity. So, avoiding noticeable hotspots is a standard technique in secure processor design.
The 4KSd core can be used as a secure second core alongside a 24K core as host, providing digital rights management and certificate handling. As this requires minimal caches, the core can be a negligible 1.5 mm2.
Another option is to use the 4KSd core as a secure system controller. This can save area in the SoC, but requires secure applications to have a higher level of privilege than the operating system.
As most operating systems (OSs) run in kernel mode, it means that the OS has to be ported to run in supervisor mode, leaving the secure applications to run in the kernel mode. This allows the same core to be used for non-secure functions, for example in a point of sale terminal, and then use the kernel mode for a secure application to handle the payment.
A core designed from the ground up for security provides the best platform for these additional technologies and enables the design of secure SoCs capable of running backward- and forward-compatible applications. Only a system-wide approach can make the next generation of devices truly secure. With secure SoC software and hardware, SoC devices can be made as secure as possible without the need for redesigning and rewriting code and introducing more costs.