Though many segments of the electronics industry have slowed, designers bank on the availability of new technologies and leading-edge chips to stimulate the development of faster computers, better communications systems, and much more. With research and development efforts moving forward, a bumper crop of outstanding papers will be presented at this week's IEEE International Solid-State Circuits Conference in San Francisco (www.isscc.org).
In communications systems, one of the most critical building blocks is the voltage-controlled oscillator (VCO), since it delivers the key operating frequency and must be extremely stable. Many of the papers in Session 17 examine the design of high-performance voltage-controlled oscillators in CMOS. One novel design developed at the University of Michigan, Ann Arbor, combines a cross-coupled CMOS oscillator and an on-chip integrated transformer (see the figure). The VCO delivers its 1.7-GHz signal with a phase noise of -137, -142, and -152 dBc/Hz at 600 kHz, 1 MHz, and 3 MHz, from the carrier, respectively.
Although made with CMOS, the VCO is designed to be co-integrated in a biCMOS process. And, the complementary cross-coupled topology has a lower phase noise than an NMOS-only implementation. Additionally, the availability of the PMOS transistors lets the transformer be driven differentially, minimizing the effects of transformer parasitics.
By shrinking design features down to 0.12 µm, researchers at Infineon have crafted a 51-GHz VCO that operates at 1 V and consumes just 1 mW. Detailed in Paper 17.8, the oscillator uses NMOS transistors as varactors. The resulting VCO phase noise at a 1-MHz offset from the 51.6-GHz carrier is -85 dBc/Hz.
In wireless communications, many papers in Sessions 5 and 7 demonstrate co-integration of the RF radio transceiver and the digital baseband controller into a single-chip system. Paper 5.1 describes a Bluetooth radio implemented in 0.18-µm CMOS that was jointly developed by Ericsson Microelectronics, Swindon, U.K., and STMicroelectronics, Crolles, France. The radio portion consumes only 30% to 50% of the power versus previous Bluetooth transceivers.
Furthermore, the radio portion occupies just 5.5 mm2 of silicon. This is considerably less than most other Bluetooth radio solutions, and less than 25% of the total area of the complete transceiver. The small area is achieved via a process that enables building devices with two different oxide thicknesses. Two extra mask steps create a high-Q metal-metal capacitor and a buried N- layer to better isolate MOS devices from the substrate.
The second paper in Session 5, presented by Silicon Wave Corp., San Diego, Calif., reveals how the combination of silicon-on-insulator (SOI) technology and a bipolar-CMOS (biCMOS) process creates a direct-conversion Bluetooth transceiver. The chip integrates the entire analog front-end transmit and receive functions and the digital modem logic, while avoiding three well-known problems associated with direct-conversion architectures.
First, the circuit digitally removes dc offsets that accumulate as signals move through the analog front end. Then, even-order distortion is minimized by using an off-chip balun and on-chip fully differential signal paths. Finally, digital techniques calibrate out self-mixing of spurious local-oscillator leakage to the RF input port.
Also, Paper 5.3 details a two-chip Bluetooth solution by Transilica Inc., San Diego, Calif. Designed for minimal chip area, it has an enhanced 8051-compatible microcontroller core rather than a 32-bit core in its baseband controller chip. The full baseband controller fits in just over 6 mm2.
The RF radio chip consumes just over 10 mm2 of silicon. By incorporating an embedded calibration state machine that autotunes a 2-MHz, five-pole quadrature complex IF filter, it eliminates the requirement for external filters.
A digital channel-selection filter is at the heart of a Bluetooth RF front-end chip described in Paper 5.5 by Hitachi Ltd., Tokyo. The digital filter eliminates the large capacitor that a high-Q analog filter would normally require. The chip area of the RF front end is considerably smaller than previous analog designs—just 11.22 mm2 when fabricated in 0.35-µm biCMOS.
Cranking CMOS To 5 GHz Pushing performance up to 5 GHz to meet the requirements of the 802.11a wireless LAN specifications, designers from Atheros Communications, Sunnyvale, Calif., and Stanford University, Stanford, Calif., crafted a single-chip CMOS transceiver. Paper 5.4 describes the RF portion of the chip set, while Paper 7.2 presents the combo baseband controller and media-access controller chip.