Electronic Design

Key Tools Drive Logarithmic Scheme

To craft the QSMath blocks, QSigma employs a structured design flow and a suite of proprietary tools.

One tool, the System Requirements Organizer, captures system-level requirements such as function(s), input and output format, throughput, processing time, precision, operating frequency, I/O clocking, and number of sources. Once the requirements are captured, the Matrix Analyzer identifies the required functional operations and sequential flow of data to implement the application transformation(s).

Next, the Trade-off Analyzer examines a spectrum of solutions that meet the system requirements and the necessary processing cells to implement the solution. Following that, the Target Architecture Generator creates a target architecture from the systems requirements, matrix analysis, and processing cell library, as confirmed by the Trade-off Analyzer. The Matrix Compiler then generates the optimized microcode and the required control code for the target architecture to meet the system specification. Lastly, the Control Structure Generator creates an optimized, low-system-overhead control structure and generates the global memory map for the target architecture from the control code meeting.

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