Electronic Design

Land Of The Rising Sun—And Technologies—Hosts VLSI Symposia

The IEEE 2005 Symposium on VLSI Technology will celebrate its 25th anniversary June 14-16 in Kyoto, Japan. But don't let its age fool you.

This conference will highlight cutting-edge CMOS front-end to back-end processes that use features as small as 32 nm. Attendees also can learn about the latest silicon processing and dielectric materials. And, the hottest memory cell structures for flash, magnetoresistive, and dynamic memories will be detailed in various presentations.

STRAINING FOR SUCCESS
IBM will describe a strain-enhanced CMOS process that delivers a 30% improvement in drive current on the 50-nm pMOSFETs (paper 3A-4). Next, STMicroelectronics will reveal how its researchers employ a buried strained silicon-germanium layer under the gate channel to achieve a 50% increase in drive currents for 50-nm devices (paper 10A-4).

Eight papers will illustrate advances in FinFET structures, while another nine papers will explain developments in metal-gate FET devices. Metal-gate structures are being revisited since they eliminate the gate depletion penalty in polysilicon and get the advantage of equivalent oxide-thickness scaling. Researchers from the National Chiao-Tung University in Taiwan will describe the implementation of RF MOSFETs on a flexible plastic substrate (paper 9A-4).

Scaled flash memory devices will be the subject of paper 11B-1 by Intel Corp., as cell sizes as small as 0.0315 µm2 can be achieved using 65-nm design rules. Devices such as phase-change RAMs, ferroelectric RAMs, magnetoresistive RAMs, and nanocrystal memories will be revealed in Sessions 6B and 10B.

AFTER THE SHOW
The companion IEEE Symposium on VLSI Circuits will dovetail with the technology Symposium, overlapping by one day, June 16-18. Papers there will investigate developments in memories, processor architectures, communications circuits, and analog circuits.

Samsung will present the first details of a DDR3-generation SDRAM that delivers data at 1.6 Gbits/pin (paper 23-4). STMicroelectronics will offer its 8-Mbit, SOI-based DRAM based on one-transistor storage elements (no capacitors) for embedded applications (paper 23-1).

Session 2 will examine high-speed processor architectures. Intel will show off a high-performance ARM-compatible architecture that runs at 1.5 GHz while IBM, Sony, and Toshiba will describe their latest work on the CELL processor.

Additional sessions at the Symposium on VLSI Circuits will look at advances in wireline and wireless communications and analog technology. For example, papers 22.3 and 22.4 from Hiroshima University and North Carolina State University, respectively, will detail inductive coupling schemes for wireless chip interconnections that allow data transfers at up to 2.8 Gbits/s.

2005 Symposia on VLSI Technology and Circuits
www.vlsisymposium.org
[email protected]

TAGS: Intel
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