Electronic Design

Late Papers At IEDM Describe Double-Strained Silicon, MRAMs, And Low-Leakage Transistors

Several late papers at next week's IEEE Electron Devices Meeting at the Hilton Washington and Towers in Washington, D.C., describe up-to-the-minute innovations from key industry leaders.

Researchers from Intel show off a strained silicon process that lets them optimize both p- and NMOS devices to achieve maximum circuit performance in "A 90-nm high-volume manufacturing logic technology featuring novel 45-nm gate length strained silicon CMOS transistors" (paper 11.6). Intel has already started high-volume manufacturing using the double-strained scheme. It also says that this low-cost process is highly manufacturable.

Typically, strained silicon processes focus on improving the performance of the n-channel devices, leaving the p-channel devices unchanged. In its double-optimization scheme, Intel uses two different strained silicon approaches on the same wafer to maximize the performance of the n- and p-channel devices.

For the improved p-channel devices, the researchers use an epitaxially grown silicon-germanium film embedded in the source-drain region of the 50-nm gate-length devices. The resulting transistors deliver drive currents of 800 µA/µm—a new record for p-channel devices. To perk up the n-channel devices, Intel used a silicon-nitride capping layer to induce a tensile strain in the channel region of the 45-nm devices. This improves the transistor drive current to 1.45 mA/µm.

"A 0.18-micron 4-Mbit toggling MRAM" (paper 34.6) from Motorola describes a highly scalable magnetoresistive RAM structure. The 4-Mbit chip has the highest capacity of any device yet fabricated, and it employs five levels of metal. It has a bit cell size of just 1.55 µm2 as well. The heart of this device, a new switching mode, enables users to simply toggle the cell state. A new cell architecture and bit cell structure make this mode possible.

Two more late papers discuss short-channel effects. Toshiba's work shows how a 0.7-nm thick silicon-on-insulator substrate can be used to host ultra-narrow-channel transistors that eliminate short-channel effects such as tunneling currents (paper 33.5). "Sub-10-nm planar-bulk CMOS devices using lateral junction control" (paper 20.7), presented by NEC Corp., illustrates how bulk silicon devices with channels as small as 5 nm can be fabricated so the short-channel effects can be controlled using a lateral-junction structure.

IEEE Electron Devices Meeting
www.ieee.org/conference/iedm

TAGS: Intel
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