Electronic Design

Look For The Signs

There is a point in every design process when volume, time, and cost considerations tip the scale in favor of designing with an ASIC or an FPGA. Some decisions are relatively easy. Go with an ASIC if it's a high-volume design that has an 18-month completion schedule. If you need a low-volume design in a few weeks, use FPGAs.

Increasingly, however, choosing between an ASIC or an FPGA isn't so simple. Here are some basic signs or guidelines that may make the decision a little easier.

Look at the application in which the device will be used.
Standards are continually evolving in networking, telecom, and other applications. Rapidly changing market demands also subject designs to last-minute feature-set changes. ASICs cannot easily, inexpensively, or rapidly be changed, so they aren't always good candidates where standards and features are in a state of flux.

Examine your design's thresholds.
If an FPGA can meet the proposed design's density, power, and performance thresholds, it should still be considered the silicon option. Keep in mind that most gate-array manufacturers have stopped supporting smaller process geometries below 0.35 µm. This is helping level the performance playing field for FPGAs, which are following the process technology curve down into deep-submicron territory.

Determine the time you have to complete your design and get your product to market.
Between design concept and production silicon, the overwhelming majority of time expended to complete your project will be spent in device design, validation, verification, and production. FPGA designs take less time because these steps are generally easier to complete. FPGAs are in themselves proof of silicon, further reducing validation time. Finally, they're programmable, so they minimize the risk of delays due to design changes and corrections.

Factor in logistical barriers.
Fab capacities are filling up. Consequently, most ASIC manufacturers aren't accepting any designs without minimum 100,000-unit volume guarantees. Also, consider the human factor. Not all design teams have experienced ASIC design engineers available, nor do all designers have access to sophisticated and expensive ASIC design-tool suites. Well-integrated FPGA tools are readily available from the silicon provider at little or no cost. These tools run on standard platforms and are relatively simple to use, typically requiring very short learning curves.

Measure the impact of an ASIC NRE on final product cost.
The actual cost of the die has become a relatively small portion of the total cost of the device—exceeded by initial design time, test, design rework, and package costs. With an ASIC, the most visible additional cost compared to an FPGA is the nonrecurring engineering (NRE). The manufacturing cost of an ASIC can be enormous. It's often $500,000, and this figure rapidly rises with smaller process geometries, more layers, and increasing numbers of mask sets. For example, an ASIC NRE cost of $X00,000 for 100,000 production devices adds $X.00 per unit to the chip price. Most likely, there will be additional costs associated with redesign, new masks, and silicon respins. In this case, a moderate volume of production silicon makes the ASIC an uneconomical proposition. On the other hand, an FPGA can be reworked very quickly and cheaply. It also doesn't have any initial or follow-on NRE costs.

Ultimately, foundry and design resource limitations may increasingly influence your decision. In very high volumes, ASICs are still your default choice. But FPGAs will continue to get you to market faster, and they're much closer to cost parity with gate arrays than they were in the past.

Contributed by Behrooz Zahiri, director of software and design applications marketing, Actel Corp.

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