Electronic Design

Memory Fault Detection IP Meets International Safety-Critical Standards

A family of fault supervisory intellectual property (IP) from Yogitech offers fault detection for memory subsystems in safety-critical systems. The detection level is certified by TUV SUD to comply with the risk level SIL3 standards of IEC 61508. Called fRMEM, the IP is available for SRAM connected to the system bus, Tightly Coupled Memories, caches, and non-volatile memories, like flash, NAND flash, and EEPROM. The fRMEM IP supports interoperability with external built-in self-test and built-in self-repair modules.

Fault detection in memories typically is addressed by error-detection codes and error-correction codes (EDC and ECC), both of which have inherent limitations that prevent compliance with SIL3 when used alone, according to Yogitech. Adding the fRMEM IP on top of EDC/ECC techniques brings the system up to SIL3 standards for use in safety-critical systems such as vehicle braking control. The IP’s Two-Memory Architecture allows flexible partitioning of data in pages with selectable protection levels, so designers can reduce area overhead. Also, the Fast-Track technique eliminates the timing overhead introduced by EDC/ECC, enabling the fastest operating frequency with no modification of either the CPU logic or the memory controller.

The Scrubbing technique, a low-power background task that scans the memory, maintains the protection level and decreases the failure in time (FIT) by catching silent faults. Finally, the Distributed MPU provides local memory protection by tacking system-level hardware and software faults. Contact the company for pricing and availability information. For more details, checkout www.fr.yogitech.com.

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