Electronic Design

Minimize clock-to-output delays in CPLD designs

Minimizing clock-to-output (tco) delays in a CPLD-based design may permit use of a slower, lower-cost CPLD. The example design shown is a state-machine implemented using a CPLD that operates as an interface between a memory-mapped peripheral and an Intel 80960 processor. The state machine controls the peripheral’s chip-select, read, and write lines, as well as the 80960’s ready-recover (RDYRCV) line.

The example uses a Cypress CY7C371i CPLD. Because the state machine has to operate at 25 MHz, the slowest speed-grade variant of the part was selected. The initial implementation of the state machine shows clock-to-output delays of 24 ns, but the design requires the delays to be less than 15 ns. So what can we do now?

First, we realize that the 24-ns delays represent second-pass (tco2) clock-to-output delays; that is, they’re due to an additional pass through the CPLD’s logic block to decode the outputs (Fig. 1). So, a higher-speed (lower tco2) CPLD can be used. A more clever approach, however, would be to encode the state-machine outputs within the state bits (Fig. 2). This eliminates the need for output decoding logic and guarantees that the outputs are available at the 10-ns tco specified on the data sheet for the slowest part (rather than at its 24-ns tco2).

Encoding the outputs within the state assignments is a straightforward procedure. First create a table matching each state with the desired outputs. Then identify the largest number of states with the same set of outputs⇓in our example, there are three (note the four 1’s in Output rows 1, 8, and 15 in the table). Finally, create a unique encoding for each state: In this example, an additional two bits are required.

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