Moore’s Law has been an influential parameter in driving IC performance forward. For decades, the number of transistors per circuit has doubled about every two years. But is this pace about to be overtaken?
Developers of the 14-nm process and FinFET technology think so. Intel, IBM, Toshiba, and Samsung are adopting 14-nm processes and moving toward the mass production of FinFET technology as quickly as their R&D legs will carry them.
FinFET technology, a term coined by researchers at the University of California at Berkeley, promises some impressive performance advantages including stricter control of short channel effects in a submicron regime and lower off-state current.
Also, the technology will allow a single transistor to act as a multi-gate device. The use of experimental gate stack materials and device architectures could significantly influence analog device properties as well.
IBM Makes A Move
IBM is already committed to moving to FinFETs based on silicon-on-insulator (SOI) wafers at the 14-nm node. In fact, the company intends to employ SOI for all of its 14-nm products, including the server processors it uses internally and the ASICs it makes for itself and its customers.
Speaking at the Common Platform Technology Forum recently, IBM Semiconductor Research Centre vice president Gary Patton explained how SOI offers advantages that bulk silicon wafers do not have.
“Process complexity is reduced because the buried oxide layer creates a built-in etch stop, which makes etching very simple. And, the cost issues go away at the 14-nm node,” he said.
Fundamentally, this means the reduced number of process steps involved in a 14-nm process offsets the cost of the SOI wafer. A further advantage of SOI is its high immunity to soft error incidence.
IBM has already developed DRAM devices with its SOI technology. The company is right to think that carrying this forward to vertically configured devices will be relatively simple.
The Fishkill Alliance of companies, including Samsung, GlobalFoundries, and Toshiba, is expected to go for bulk production of FinFETs at the 14-nm node. IBM also is participating in an alliance with STMicroelectronics and Leti to develop a planar SOI technology that offers fully depleted technology.
In a related move, research organisation Imec has developed an early-version process development kit (PDK) for 14-nm logic chips. This PDK targets the introduction of a number of new technologies, such as FinFET technology and extreme ultraviolet (EUV) lithography.
Imec and its partners are developing a 14-nm test chip to be released later this year using the PDK. This chip will facilitate interconnect, process, litho elements, and circuit performance implemented in the 14-nm node.
In contrast to the “full steam ahead” 14-nm position of these companies, the Taiwan Semiconductor Manufacturing Company (TSMC) may have already announced its plans to catch up on FinFET technology. However, it has stipulated that the technology won’t be available to its customers until the 14-nm node becomes the mainstream process.
Back in 2002, TSMC demonstrated a product it dubbed the Omega FinFET, a 25-nm transistor that could operate on 0.7 V. However, this demonstration did not lead to a commercial implementation.
So, it’s reasonable to say the speed at which companies are moving toward 14 nm FinFET technology could mean IC development is poised to overtake Moore’s Law and its original assertion that the number of transistors on a circuit will double every two years.
There are also rumours that Intel is already looking at how it will progress beyond 14 nm to 8 nm in a few years. Is it time for Moore’s Law to move into the slow lane? Maybe. The only doubt here is that at 8 nm, the theoretical operation limits of silicon will have been passed. So what happens then? The answer has to lie in graphene.