Electronic Design

Multifunctional HyperTransport

HyperTransport (HT) is a high-speed, low-latency, point-to-point link. The current design handles peak rates of 102.4 Gbits/s. It has support from a wide range of suppliers and is incorporated into processor chips, such as Broadcom's BCM1125H, BCM1250, and BCM1400, AMD's Opteron, and various HT bridge chips (see www.hypertransport.org).

The HyperTransport standard defines data width links from 2 to 32 bits, with most systems implemented with 8- or 16-bit interfaces. The interface uses low-voltage differential signaling (LVDS).

The basic HyperTransport standard provides communication between HyperTransport devices. Building on the base standard, the coherent transport protocol supports a cache-coherent nonuniform memory architecture (ccNUMA) that provides a distributed memory architecture. Local memory is accessed more quickly by a processor than nonlocal memory.

Another HyperTransport extension is packet-streaming support. This adds 16 streaming virtual point-to-point channels. It enables HyperTransport links to bridge SPI-4 traffic. Normally the HyperTransport device has an SPI-4 interface to a channelized framer.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish