What is NAND flash memory?
NAND flash is a type of nonvolatile memory that is accessed like a mass storage device (e.g., a hard drive). A form of electronically erasable programmable readonly memory (EEPROM), NAND flash is programmed, erased, and reprogrammed in large blocks. It's called NAND because at the circuit level, it's similar to the NAND logic function. Another type of flash is NOR flash (Fig. 1).
What does the structure of a NAND cell look like?
A flash cell comprises two transistor gates separated by a thin dielectric oxide layer (Fig. 2). One gate is called the floating gate and the other the control gate. An insulating dielectric surrounds the floating gate. When there is no excess of electrons on the floating gate, the cell is in the erased ("1") state and has a relatively low threshold ("turn on") voltage. In the programmed ("0") state, an excess number of electrons on the floating gate increases the cell's threshold voltage.
When a cell stores one bit per cell, it's called a single-level cell (SLC). But a cell may hold more than one bit by "storing" different amounts of charge. In an SLC, a single voltage threshold distinguishes two charge levels, resulting in 1 bit of storage. A multilevel cell (MLC) uses multiple voltage thresholds.
How is NAND flash read/ written and used in a typical embedded system?
With NAND flash, data is written and read one "page" at a time. Flash memory must be erased prior to rewriting, and this is performed one "block" at a time. A block comprises a fixed number of sequential pages.
NAND isn't addressed like a typical memory. Instead, it has an indirect interface that is accessed sequentially using a file system much like how a mass storage device such as a hard-disk drive is accessed. As such, random access of bytes is not possible.
However, NAND flash excels at sequential block access. Its program and erase speeds are much faster than NOR flash devices.
What are ECC and wear leveling, and why are they needed?
Flash cells have a limited number of write/erase cycles. So to prolong the life of flash, a technique called "wear leveling" is applied in which data is spread across various physical locations of the memory.
Flash memory is also shipped with bad blocks. The bad blocks shipped with the product plus those that wear out over time must be managed. Since bad blocks must be managed and wear leveling implemented, a physical-to-logical addressing scheme must be implemented. A controller dynamically assigns a physical address within the storage media from logical ones to store this data.
ECC (error-correcting code) is used to correct bit errors that can occur during normal operation as well as bit errors that occur due to charge loss/gain that develop over time. ECC circuitry (external to the NAND) is used to correct errors when reading data back from the NAND flash. ECC is necessary to maintain program and data integrity in computer systems.
What are some system-level issues encountered when integrating NAND flash?
Flash requires a file system, logical-to-physical address mapping, ECC, wear leveling, and bad block management, which are typically handled via the host processor. Because features such as page size and block size differ between manufacturers, and even between generations of flash from the same vendor, integrating flash into a system becomes even more challenging. This management overhead can burden the host processor.
The alternative is to use an integrated control unit with firmware dedicated to managing the flash access, wear leveling, ECC, and other flash overhead. The advantage of this approach is simple: Using a dedicated control unit offloads most of the flash management overhead from the host, freeing it up to perform other functions, and eliminates the need for a flash filing system. Also, built-in ECC generated by the vendor guarantees the error-correcting requirements are met.
This can be accomplished with a single package containing both the flash and the controller (Fig. 3).