Electronic Design

The Network Processor De-Evolution Has Begun

We are witnessing a sea change within the communications silicon industry. NPU (network processing unit) architectures are moving away from the monolithic, proprietary processing cores that have dominated the landscape for the last two years. Instead of an evolution into more complex architectures, as one would expect, we’re seeing a "de-evolution" or devolution of the NPU to more straightforward, standards-based processing cores using such architectures as PowerPC and MIPS. (Author photo)

Proprietary NPUs simply require too many resources and provide too little return. Creating an NPU requires the development of proprietary processing cores, tools, development environments, and communication and system software, not to mention the technical and marketing evangelism that accompany these activities–none of which is sustainable by today’s fragmented communications market.

In addition, NPUs take significant performance hits when trying to handle specialized functions like encryption. As a result, many OEMs have turned to off-chip merchant silicon to handle tasks requiring the functionality and performance that only hard-wired silicon brings to the table. This reduces the need for a complex processing core.

So, what exactly will the NPU devolve into? Undoubtedly there will be varying forms from many vendors. But to succeed, all of these new devices will share two key characteristics.

First, programmability will be key to any successful next-generation device. Developers will have a set of common tools and programming environments that work across a wide variety of programmable devices.

The second characteristic will be more defining. Devolved NPUs will be able to use the enormous amount of code and applications that already exist for standard architectures such as PowerPC and MIPS. IBM’s selection of PowerPC for its next-generation NPU device clearly reflects this trend, and other vendors will surely follow suit.

For the systems OEM, standards-based technology will likely have a favorable impact on overall cost. A programmable, open-architecture NPU based on a standard processing core will be much easier to design around, as developers will spend fewer cycles creating software for a complex architecture. Thus, a migration path to next-generation devices can more easily be planned, reducing risk. Code developed on standards-based technology will be more portable, further reducing development time.

Finally, OEMs will be able to pick and choose the merchant silicon best suited to their system. Traffic managers, classifiers, security accelerators, T-CAMs, and other application-specific silicon are already on the market, and many are being incorporated into designs using this approach. Many OEMs have already rejected closed, proprietary architectures, as they fear being locked into a relationship with a single vendor.

Devolution will be a healthy and much needed return to sanity for the communications silicon industry. OEMs will retain the salient benefits of the NPU, programmability and code reuse, while larger NPU vendors can return to a sustainable business model. Just as we moved from the ASIC + CPU to the proprietary NPU, the time has come to move to standards-based, programmable silicon, a model that will once again transform the communications silicon industry into a growing market.

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