The Octeon EXP processors combine data-plane and control-plane processing into single-chip solutions. They also can operate at multigigabit rates using a standard C/C++ software programming model. They're based on an architecture that uses multiple MIPS64 processor cores, release 2 of the MIPS instruction-set architecture.
Developed by Cavium Neworks, the EXP series will find homes in networking and storage applications (see the figure). The chips should reduce a typical system's bill-of-materials cost by a factor of two. At the same time, they will be able to handle competitive data throughputs ranging from 2 to 10 Gbits/s and perform Internet Protocol forwarding at up to 20 million packets/s.
These scalable chips deliver up to 19.2 billion instructions/s of general-purpose processing across four to 16 dual-issue 64-bit MIPS CPU cores. Designed from the ground up, each 600-MHz MIPS core includes instruction additions to accellerate packet operations. Each core also includes a 32-kbyte instruction cache, an 8-kbyte data cache, a 32-entry translation look-aside buffer, and a 2-kbyte write-back buffer.
To accelerate network throughput, Cavium integrated dedicated packet processors for layer 2 through 4 parsing, error checking, tagging, and memory allocation. Three high-performance memory controllers on the chip provide high data bandwidth. One memory controller provides a 144-bit wide ECC-protected (error checking and correction) Double-Data-Rate II DRAM port that transfers data at up to 800 Mbits/s. The other memory controller ports support 18-bit wide low-latency RLDRAM2/FCDRAM.
These ports can connect to ternary content-addressable memories for offloading lookups to an external hardware-device. For higher-layer data-plane processing, the chips include dedicated hardware for TCP acceleration and flow management to scale performance across multiple cores.
To reduce system costs, Cavium integrated multiple standard external network interfaces. Four to eight Ethernet ports (RGMII), or dual SPI-4.2 interfaces, as well as a host/slave PCI-X 64-bit/133-MHz interface are available for network and control functions. Also available are general-purpose I/O lines, a flash-memory interface, dual UARTs, and a two-wire serial interface.
The Octeon EXP chips come in versions with four, eight, 12, or 16 dual-core MIPS CPUs and with four or eight Ethernet ports. Power consumption ranges from about 10 W for the four-CPU chip to about 30 W for the 16-CPU version. The standard software programming model includes C/C++ as well as MIPS64 and MIPS32 compatibility.
Linux operating-system support, a GNU tool-chain and development environment, and support for third-party commercial operating systems and tools make it easy to develop the software to handle networking and storage applications.
Prices range from $350 to $650 each in lots of 10,000. Samples are immediately available, along with a development kit that includes a simulator, tool-chain, and reference applications.
Cavium Networks Inc.