Electronic Design

Outpace Your Competitors With A Solid IP Plan

INTELLECTUAL PROPERTY (IP) IS ESSENTIAL IN SYSTEM AND SYSTEM-ON-A-CHIP (SoC) DESIGN.
It reduces design time, in turn accelerating time-to-market. This is particularly true in the SoC market, where IP is now the most valuable aspect of just about every chip manufactured today.

IP takes many forms in the semiconductor industry, like basic manufacturing know-how (from silicon materials to packaged chips). It also involves the design of complex logic or analog functions, such as microprocessor cores or phase-locked loops. IP even extends into the software or firmware used to define chip functions, as well as into the end applications executed by the chip.

Designers could use a novel process, a transistor enhancement, or a unique IP block to deliver higher performance, better density, lower power, lower cost, or any kind of advantage to beat the competition. Such an advantage could be worth millions of dollars if the technology provides that edge in the competitive marketplace.

On the other hand, multiple vendors offer plenty of commodity IP blocks for just a few thousand dollars. Companies can purchase or license these blocks to reduce the overall SoC design effort. This saves designers time they would otherwise spend crafting new implementations of common functions, such as direct-memory-access controllers, register files, DRAM controllers, or parallel PCI ports.

The greater complexity of systems being implemented on a chip, plus shorter time-to-market requirements, makes circuit IP more crucial than ever. Today, SoC design would take far too long if every function had to be designed from the basic gate or transistor building blocks. This is especially true for the multi-megagate custom chips under development by many semiconductor manufacturers or fabless companies.

Licensing or purchasing circuit IP and incorporating it into a new design can save hundreds to thousands of hours of circuit design and validation time. Such savings are also possible when using internally created IP (see the figure).

RULES? WHAT RULES?
Until recently, few formal guidelines defined what an IP supplier should include as part of the "package" it delivers to a customer. The IP by itself, in the form of an RTL description, won't meet a chip designer's needs. Through the Virtual Socket Interface Alliance (VSIA), many companies have worked side by side to come up with a set of common guidelines and standards for IP.

Some of VSIA's work relates to defining what should be supplied along with the blocks of digital IP. Other work covers analog and mixed-signal IP blocks. The group has also tackled test and verification issues and investigated IP security. So a block of IP isn't just an RTL description, it also must include many areas of support. Basic documentation that describes its operation and interfaces and verification models to speed final functional testing are just two examples.

Many kinds of companies offer blocks of IP. TriCN Inc. and GDA Technologies are among the small firms with a handful of engineers. Then, there are divisions of billion-dollar organizations like Cadence Design Systems, Mentor Graphics, and Synopsys. ARM, MIPS Technologies, and Virage Logic lead the large independent suppliers. ASIC vendors Freescale Semiconductor, IBM, LSI Logic, and Toshiba are some of the fabrication-independent suppliers. And don't forget the foundries, like TSMC and UMC, that not only offer third-party IP libraries, but are also starting to offer optimized IP libraries tuned for use on their own manufacturing processes. (For a complete list of the companies cited in this issue's IP series and their respective URLs, see the online version of this article at www.elecdesign.com, ED Online 10085.)

There's always a certain amount of risk when integrating a block of IP into an SoC design. According to research done by Collett International Research (www.collett.com), about 70% of all new IC designs have a functional error that may require a silicon re-spin. Designers must consider this figure in their cost analysis as they decide whether to craft their own core (with the potential for a functional error) or incorporate a third-party block of IP.

Designers choosing to go with a third-party vendor need to ask some key questions, too. Is there a guarantee behind the IP's claimed functionality? How much aftermarket support is available? Are all facets related to the IP--design files, simulation files, test and verification files, and test silicon--available? Does the vendor have any customers with proven chip designs that incorporate the IP? Synopsys offers a return-on-investment calculator and white paper on modeling the total cost of ownership for semiconductor IP at www.synopsys.com/cgi-bin/dwiproi_calc/reg1.cgi.

MINIMIZING YOUR RISK
Designers who proceed without answering these questions risk a non-functioning chip design, which balloons time and money costs. If the chip doesn't work the first time out, diagnosis, correction, and refabrication could take months.

If the chip's market entry is delayed, the company stands to lose market share. Designers must then consider a number of factors before choosing an IP vendor. For instance, "buyer beware" is certainly a good rule to follow. Even budget-priced IP might require more work than expected to integrate it into a design. VSIA's standards and guidelines provide a good starting point in dealing with IP issues.

In today's megagate SoC designs based on 130-nm design rules, Phil Dworsky, director of marketing for DesignWare IP at Synopsys, suggests that close to 86% of an SoC's nonmemory transistors are reused. They're part of an IP block that's either licensed from a third-party supplier or an internally developed block.

The most common form of IP is called "soft" IP. It usually comes in the form of a generic process-independent RTL file that can be readily integrated into the main design file. Some IP also is available as "hard" blocks, which usually means the RTL file was already synthesized and placed based on a specific set of process design rules. Although this makes the block manufacturer-specific, the block can deliver the best performance because the design is pre-optimized.

Two main areas of concern arise when interconnecting blocks of IP. First, there's the signal interface between the core and the system. Second, there's the on-chip bus used to interconnect the blocks together. Some good initial results have come from VSIA and other groups like the Open Core Protocol International Partnership (OCP-IP) in attempts to define a standard interface to a core (a "socket").

OCP-IP hopes to make the Open Core Protocol the most widely used and adopted socket interface for SoC design. The group provides tools and services for the convenient implementation, maintenance, and support of the standard socket interface. Sonics Inc. and a few other companies also have tools that can encapsulate a block of IP and provide a "standard" interface. As a result, the core can be connected to a well-defined on-chip bus.

The on-chip interconnect bus is open for much debate. No two system requirements are the same. Consequently, it's nearly impossible to define an on-chip bus that will satisfy all designers. VSIA agreed that no single bus standard will encompass all needs. Its bus interconnect standard permits multiple on-chip bus solutions.

Many companies have adopted the ARM AMBA bus, an open-specification on-chip bus originally targeted at ARM processor cores, as a generic interconnect solution. By designing to the standard AMBA interface, IP developers can implement and test modules without prior knowledge of the system, and then the component can ultimately be integrated.

ADVANCED IP PIQUING INTEREST
So what's hot in the IP community? Designers are looking for advanced cores like ARM, MIPS, PowerPC, ARC, and Tensilica. They're also keen on memory blocks such as SRAM, FIFO, and embedded DRAM. Specialized I/O and communications interfaces, e.g. SERDES, PCI Express, and Ethernet, are popular as well.

Plenty of other IP is available too: DSP engines, graphics controllers, MPEG encoders/decoders, bus structures like AMBA/AHB, and other on-chip buses. Groups like the Virtual Component Exchange and Design and Reuse SA provide online databases of licensable IP available from many vendors.

Designers can tap many sources for SRAM-based blocks of memory IP. But SRAM densities aren't adequate to handle some of the most memory-intensive designs. This opens the door to companies offering blocks of embeddable DRAM that can be integrated on an ASIC along with all logic blocks.

IP also plays a vital role in highly integrated FPGA solutions. Processor cores are in high demand, as are specialized I/O functions like PCI Express, high-speed serial interfaces, double-data-rate DRAM controllers, and standard parallel PCI buses. Many third-party IP suppliers offer a broad array of circuit functions that supplement the large catalog of blocks available from FPGA vendors.

ADVANCED IP PIQUING INTEREST
So what's hot in the IP community? Designers are looking for advanced cores like ARM, MIPS, PowerPC, ARC, and Tensilica. They're also keen on memory blocks such as SRAM, FIFO, and embedded DRAM. Specialized I/O and communications interfaces, e.g. SERDES, PCI Express, and Ethernet, are popular as well.

Plenty of other IP is available too: DSP engines, graphics controllers, MPEG encoders/decoders, bus structures like AMBA/AHB, and other on-chip buses. Groups like the Virtual Component Exchange and Design and Reuse SA provide online databases of licensable IP available from many vendors.

Designers can tap many sources for SRAM-based blocks of memory IP. But SRAM densities aren't adequate to handle some of the most memory-intensive designs. This opens the door to companies offering blocks of embeddable DRAM that can be integrated on an ASIC along with all logic blocks.

IP also plays a vital role in highly integrated FPGA solutions. Processor cores are in high demand, as are specialized I/O functions like PCI Express, high-speed serial interfaces, double-data-rate DRAM controllers, and standard parallel PCI buses. Many third-party IP suppliers offer a broad array of circuit functions that supplement the large catalog of blocks available from FPGA vendors.

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