Electronic Design

Platforms Get Extreme For Storage, High-Speed I/O

Novel platform ASICs meet storage and communications system demands by delivering plenty of memory and multigigabit I/O ports.

Novel platform ASICs meet storage and communications system demands by delivering plenty of memory and multigigabit I/O ports.

Embedded applications in storage and communications crave sizable amounts of memory, and speed is always a concern. The three latest Xtreme series additions to the RapidChip platform ASIC family answer that call by combining a multitude of memory blocks and high-speed serial channels. Also, developer LSI Logic has added new members to its QS Integrator series, which targets systems that make extensive use of high-speed serial protocols.

The Xtreme family welcomes the RC11XT410, 440, and 555 slices, which offer as many as 32 serializer/deserializer (SERDES) channels. Each channel can handle multiple interface standards at data rates of up to 4.25 Gbits/s. The slices are optimized for PCI Express designs with four-, eight-, and 16-lane configurations.

The R11XT410 packs I/O support for DDR2 and QDR memories, four quad-channel GigaBlaze serial interfaces, 3 million usable gates, and 1.4 Mbits of SRAM. With 3.5 million gates, 2.4 Mbits of SRAM, and twice the number of GigaBlaze serial interfaces, the 440 slice delivers additional logic and memory resources to support more complex designs. The 555 leverages the flexibility of LSI's new Hydra high-speed transceiver building blocks.

The Hydra transceivers support serial data rates ranging from 100 Mbits/s to 3.2 Gbits/s, meeting the needs of XAUI, serial and parallel Rapid I/O, Gigabit Ethernet, SPI 4.2, SPI-5, and HyperTransport interfaces. The Hydra cores offer full SERDES capabilities, including clock- and data-recovery circuitry on the receiver to recover both clock and data from a received bit stream. Alternately, the core may be configured to support source-synchronous interfaces, in which a separate clock is sent with the data.

In addition to the Hydra interfaces, the new Xtreme slices possess as many as 5 million usable gates and 2 Mbits of SRAM. All slices support the company's Landing Zone region, which can host a 32-bit ARM966 core running at 212.5 MHz.

The three new Integrator QS slices offer a more cost-sensitive solution that still brings high-speed interconnect (x1 to x4 PCI Express) via four independent lanes of GigaBlaze-based SERDES. Each is capable of up to 4.25-Gbit/s data transfers. The PCI Express data lanes can run at speeds of up to 250 MHz.

The ability to combine SERDES and high-performance logic is possible thanks to the 110-nm design rules. They ensure that developers can implement ASIC-class low-latency, high-system-performance solutions.

The IntegratorQS slices offer from 1 million to 2.9 million usable gates. They're also armed with 1.1 to 5.7 Mbits of SRAM and 171 to just over 800 I/Os. Landing Zone support is integrated for a 32-bit ARM926EJ-S CPU core, which can run at up to 200 MHz, and configurable double-data-rate SDRAM interfaces that operate at up to 200 MHz (point-to-point).

Pricing ranges from $60 to $145 each in volume production. Cost for the IntegratorQS slices starts at less than $50 each in volume (30,000 to 50,000 units).

LSI Logic Corp.
www.lsil.com

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