Wireless networking solves many of the cost problems of wired networking by requiring less infrastructure and equipment. Yet wireless networking also must grapple with its own issues. For instance, in the wireless world, protocols don't have a long lifetime. For device makers, this has meant having to constantly invest in new technologies. It also has kept the design team on an almost continuous learning curve. These problems may soon be a thing of the past, however. The IP3023 wireless network processor from Ubicom, Inc. is laying the groundwork for a world in which one chip can serve all protocols.
To understand the IP3023, first consider that it is built on an entirely new microprocessor-architecture category—the Mul-tithreaded Architecture for Software I/O (MASI). This architecture is expected to revolutionize the wireless-networking market in much the same way that CISC and RISC transformed desktop and high-performance computing. Specifically, it is designed to enable the high-performance execution of software I/O.
Obviously, software I/O implements all of the communications and control functions in software. It thereby eliminates the costly dedicated hardware I/O that can account for as much as 75% of a chip's die area. For makers of wireless-networking equipment, the bonus that it offers is inherent. Software I/O can be adapted and upgraded to meet evolving standards or demanding applications.
To achieve this I/O, five years of work and many engineering principles had to come together. The first of these techniques is determinism. MASI features deterministic execution, which allows developers to exactly time a software routine.
Secondly, MASI is a multithreaded architecture. When combined with its deterministic nature, multithreading permits each thread to operate independently with no impact from conditions among threads. As a result, each thread can be seen as a separate processor. Every thread also is programmable. This aspect allows systems to be field-upgraded as standards change.
Because it is a memory-to-memory architecture, MASI enables the processor to move inputs directly to memory. It also can move outputs directly from memory to the I/O pins in real time. Lastly, MASI requires strong bit-manipulation instructions. It may then permit individual I/O pins to be efficiently accessed.
To see how the MASI architecture's engineering techniques come together, look to the IP3023 processor (see figure). This chip features eight-way deterministic, instruction-level hardware multithreading. As a result, it can simultaneously handle eight different execution threads in its pipeline. It can even act as eight virtual microprocessors, with as many as six threads dedicated to software-I/O functions. In addition, a 64-entry scheduling table lets the developer assign a different, flexible number of MIPS to each hard-real-time (HRT) thread. Each thread can have a speed ranging from 0 to 250 MHz. Speeds are assigned in 3.9-MHz increments.
The IP3023 also flaunts zero-cycle context switching. A zero-overhead scheduler enables penalty-free multithreading. Developers can therefore take advantage of up to eight virtual processors while avoiding the typical switching penalties of general-purpose processors.
The processor features a memory-to-memory architecture that processes data directly in memory. It uses a single instruction that reads, modifies, and writes data in one cycle. This method is very efficient, as packet-processing operations only need to access data once. It saves clock cycles while reducing overall code size. The memory-to-memory architecture also eliminates load/store instructions, which are found in general-purpose OSs and required by desktop-computing architectures.
Through its strong bit manipulation, the IP3023 allows the direct access of pins from the CPU core. This feature permits the efficient manipulation of packet headers.
The IP3023 also houses an instruction set that's designed specifically for wireless networking. It uses just 41 instructions while eliminating much of the overhead associated with traditional approaches. Memory requirements are reduced by up to 95%. By discarding on-chip caches, the instruction set also leads to very low latency. With on-chip memory, the device can achieve 1 GBps of memory bandwidth.
Among the processor's other features are a 32-b data path and a clock speed of 250 MHz. It has 256 kB of code RAM and 64 kB of data RAM. A SDRAM serves as the external memory controller. The IP3023 also has four MII ports and two SerDes units.
Many of the processor's features were added to give the IP3000 family enough horsepower to implement higher-data-rate protocols, such as 802.11a/g. The IP3023 also should be able to drive high-performance wireless applications like gateways, routers, and multiprotocol access points.
In a 208-pin plastic quad flat package (PQFP), the IP3023 should begin sampling this quarter. Production is slated for the second half of this year. It will sell for $12 in 100,000-unit quantities.
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