Programmable logic is going mainstream. Programmability, or rather configurability, will no longer be confined to glue logic, datapath chips, or special processing functions. Instead, programmable logic will become the glue to extend configurable logic across the full range of digital design. System and logic design will increasingly shift to programmable ASSPs—application-specific standard parts that are configurable via programmable logic.
Programmability has always been an attractive goal. Previous constraints, like limited silicon resources, slow programmable logic, and ineffective tools, confined the reach of programmable-logic design. Today, those limitations are rapidly falling off, opening up programmable logic as a key design technology in several areas. These include programmable IP for ASICs, FPGA-enabled ASSPs, configurable microcontrollers (µCs), and programmable system-on-a-chip (SoC) platforms.
Programmable logic is slower and much larger than comparable standard-cell functions. Yet, it delivers reconfigurability—i.e., the ability to reconfigure the logic design on a finished chip. Reconfigurability is gaining importance to system and logic designers, especially standard-cell ASIC designers. With on-chip reconfigurability, they can build multiple versions of the same basic design, each targeting a different aspect of the market.
The ability to leave part of the design open to later changes is critical for ASICs that rely on rapidly evolving communications, bus, and interconnection standards. Spare logic lets designers upgrade the standing logic to match newer requirements.
Designers need to be able to fix or work around logic errors found downstream in the product cycle. With FPGA-based control, they can upgrade algorithms without doing a new mask set.
The first capability supports treating ASIC designs as programmable ASSPs that can be tailored for specific requirements. So, a single mask set can serve to drive multiple ASSP chips. This will become an increasingly important feature as the price of mask sets rises with higher silicon densities. A mask set for 0.18-µm CMOS runs around $300,000 to $350,000, one for 0.13-µ>m CMOS costs about $500,000, and a mask set for 0.1-µm CMOS could be $750,000 or more. Programmed configurability lets engineers define multiple ASSPs from a single mask set for a tre-mendous savings.
Moreover, rising silicon size and pinouts may make sufficient "white space" available in ASICs to accommodate programmable-logic IP without compromising chip design. For pin-limited ASICs, silicon real estate often is virtually free for additional IP, except for increased power and test budgets. This enables the addition of design luxuries, such as programmable logic, to large-pinout ASICs.
Two vendors, Adaptive Silicon and Actel, both field RAM-based FPGA IP for ASICs. Adaptive Silicon has developed a programmable-logic system for IP deployment with a wrapper and built-in interface. Supporting up to 25,000 ASIC system gates at clock rates up to 100 MHz, Adaptive's MultiScale Array (MSA) was designed for both control and datapath usage. It handles wide datapaths and adders (Fig. 1).
The MSA 2500 builds around a 4-bit logic slice. This slice can be configured as a 4-bit ALU with control logic and fast carry-look-ahead, or as a set of four three-input lookup tables (LUTs). A block of four slices forms a quad block, and a 4-by-4 set of quad blocks makes a hex block, the smallest deployable IP block. The FPGA has local and global routing resources.
Another FPGA IP offering is Actel's VeriCore. It's based on RAM, and it supports up to 40k programmable system gates running at up to 100-MHz rates. The basic logic cell is the logic unit, which consists of two three-input LUTs feeding into a multiplexer and a flip-flop. The logic units are organized into sets of four, with one functional group in total. A PEG consists of 64 functional groups, and it holds about 2.5k system gates. The VeriCore architecture centers on a block of PEGs that are supplemented by optional hard RAM and I/O blocks (Fig. 2). The architecture can have up to eight optional RAM blocks, with up to 73,728 RAM bits.
FPGA-based ASSPs need not be restricted to ASICs. Some vendors are combining existing programmable-logic technologies with hard IP to create their own programmable ASSPs. These include Actel, Agere (formerly Lucent Microelectronics), Cypress, and QuickLogic.
QuickLogic was one of the first programmable logic vendors to recognize the need for programmable ASSPs, especially those that integrate hard standard-cell IP with programmable logic and on-chip RAM. QuickLogic's ASSPs include QuickDSP (for DSP processing), Quick SD (serial input with a serializer/deserializer or SerDes), QuickPCI, and QuickRAM.
Such FPGAs use QuickLogic's programmable antifuse, ViaLink, and have a multiplexer-based basic logic cell with holding register bits. The Quick FPGAs provide up to 662 kgates and 83 kbits of RAM. The QuickDSP has a layered architecture, consisting of a dual-port SRAM layer, a layer of Embedded Computation Units (ECUs), an FPGA logic layer, and a bottom SRAM layer. The ECUs integrate MPY, ADD, and accumulate functions.
Agere fields what it calls its Field-Programmable System Chips (FPSCs), a combination of special hard-application IP with the company's ORCA programmable logic. Because Agere is both an ASIC house and an FPGA vendor, this combination works well. Its latest FPSC, the ORT8850, implements an eight-channel by 850-Mbit/s backplane transceiver. This chip delivers Sonet connectivity and is back-ended by an FPGA array for application logic and interfaces. The FPGA supports between 260,000 and 970,000 system gates, with internal clock rates of up to 250 MHz.
From Cypress, the Programmable System Interconnect (PSI) is another programmable ASSP. Designed to support high-speed serial interconnections, such as serial backplanes, the PSI chips integrate up to eight serial channels with a SerDes, a set of datapath registers, and a CPLD. The chip handles 2.5-Gbit/s serial data rates. The back-end CPD supplies up to 200k usable gates and up to 480 kbits of integrated memory (with up to 96 kbits of dual-port or FIFO RAM).
Vendors of µCs have done well supplying ASSP variants of proprietary cores. For example, Motorola's variants range from the 6805 to the PowerQUICC, with each member deploying a specific combination of memory, peripherals, and special circuits. Adding programmable logic and programmed configurability to µCs could minimize the number of physical chip variations while maximizing the number of fieldable chip combinations.
To date, no mainstream µC vendor has announced a reconfigurable ASSP product. But that day is coming fast. Exploratory talks are under way with FPGA IP vendors, like Adaptive Silicon, to incorporate programmable arrays into the µC vendors' ASSP chips.
Programmable µC-based ASSPs have now emerged, although not from classic µC vendors. Instead, programmable-logic vendors have launched their own configurable µCs. Designers at Atmel and Cypress Semiconductor have created their own 8-bit µprocessor CPUs that perform 16-bit arithmetic and support easy C compilation.
Atmel's FPSLIC defines a very interesting µC. It integrates an 8-bit AVR RISC processor, some standard µC peripherals (two UARTs, two 8-bit and one 16-bit timer/counters), 32 kbytes of SRAM (I and D RAM), a hardware multiplier unit, and up to 40k SRAM-based FPGA gates (Fig. 3). The FPGA has up to 18 kbits of free RAM.
The AVR CPU runs from both on-chip SRAM and external memory. The on-chip memory controller supports both CPU execution and dynamic configuration of the on-chip FPGA. By ping-ponging between RAM banks, the logic array can be dynamically updated. Running at 40 MHz, the 8-bit CPU delivers 30 MIPS. It supports 16-bit arithmetic and uses a 32- by 8-bit register file.
Cypress takes a different approach with its pSoC, a µC ASSP that's more like a µC supplemented with programmable I/O configurations. The ASSP's I/O is built from a set of multiple building blocks. These are interconnected via programmable logic, using programmable multiplexers, to deliver a specific set of I/O peripheral functions. The digital programmed peripherals include timers/counters, serial ports, and CRC generators, while the analog peripherals include digital-to-analog converters (DACs), analog-to-digital converters (ADCs), analog drivers, and high-/low-/bandpass filters. The CPU runs at 24 MHz and supports an 8-by-8 multiply with a 32-bit accumulator. The chip handles up to 16 kbytes of flash memory and up to 256 kbytes of SRAM.
Another programmable µC is Tri-scend's CSoC platform. It integrates a standard processor core, an 80C51 or an ARM A7, with an on-chip bus, the CSL bus, and an SRAM FPGA. Supporting different processors, it provides a special CSL processor socket and a CPU-independent CSL bus. The CPU is supported by up to 40k FPGA gates, as well as 8 kbytes of cache and 16 kbytes of scratchpad SRAM, a four-channel DMA controller, a memory interface unit to off-chip memory, and standard peripherals (two timers, two UARTs, and a watchdog timer).
More CSoC processors are on the way. Hitachi has cut a deal with Triscend to implement its own CSoC, based on its SuperH 32-bit RISC processor. Plus, Triscend plans to port additional CPUs to its CSoC platform.
Many of the larger FPGA families offer a full digital-design platform for high-end SoC designs. (Smaller FPGAs support low-end SoCs.) Designers receive the necessary memory, special logic (multipliers, carry-look-ahead circuits, etc.), and I/O to complete their designs. These platform-level FPGAs integrate 1M to 10M programmable system gates, up to 3 Mbits of RAM, and special carry-look-ahead or multiplier functions. They clock in with I/O serial rates out to 622 Mbits/s and beyond. Internal clock rates run up to 250 Mbits/s. Some FPGA vendors fielding these high-end, SoC-level FPGAs are Altera, QuickLogic, and Xilinx.
Vendors are turning to hard-IP on-chip RISCs for processing power. These CPUs include the ARM, MIPS, and Power PC 32-bit RISC processors. For efficiency, these CPUs are integrated with an on-chip busing system, like the ARM AMBA or IBM CoreConnect. Such systems define a high-performance systems bus, supplemented with a slower, simpler systems bus for slower peripherals.
The king of the programmable-SoC hill is Xilinx, which dominates the high-end of the programmable logic market—over 50% of the 1999 PLD market, according to IDC. Xilinx's latest offering, Virtex II, targets SoC platform design. The RAM-based FPGA supports up to 6 Mgates. Supporting features include 16 clock networks, 12 digital clock managers, up to 3.5 Mbits of RAM/ROM, 18- by 18-bit multipliers, a full set of I/O interfaces, and 122,980 kbits of LUT memory. The on-chip routing resources were extended to handle larger datapaths.
Virtex II supports add-on IP, too. Any programmable-gate area can be re-moved and then substituted by hard IP. This IP can use the same local and hierarchical routing resources as did the logic that it replaced.
Altera also is in the programmable-SoC competition with its Apex series, which fields up to 2.4 Mgates. These FPGAs are RAM-based, built on a LUT-based logic cell, with hierarchical routing to handle large datapath widths. They can tolerate 200-MHz internal clock rates, and up to 622 MHz for serial I/O. The architecture will support hard ARM, MIPS IP cores, and the AMBA bus.
Another product line, Altera's Excalibur FPGA, supports high-end SoC design. This is a SRAM-based FPGA using LUT-based logic cells (Fig. 4). It handles up to 1M usable gates, with up to 128 kbytes of dual-port SRAM. Excalibur FPGAs can incorporate a MIPS or ARM µprocessor. It uses ARM's AMBA busing system to integrate the processor with on-chip peripherals and logic.
Programmable logic started out as a mechanism to implement control logic. As logic densities increased and newer CPLD/FPGA technologies emerged, programmable logic increasingly took on more datapath chores. Today's higher-density CPLDs and FPGAs have the majority of their logic dedicated to datapath functions. In many designs (50 kgates and over), at least 90% to 95% of the implemented logic performs datapath functions. Most designs, then, consist of dataflow datapaths controlled by a small subset of control logic.
Early combinatorial PALs and later PLDs have given way to CPLDs and FPGAs. PLDs are still around, but today's CPLDs and FPGAs deliver higher gate densities and clock rates. CPLDs tend to follow the PLD model, building on logic blocks of combinatorial logic and flip-flops interconnected via a central switch.
In contrast, FPGAs usually rely on distributed and hierarchical routing resources, connecting logic cells. These logic-cell implementations vary from one vendor to the next. Some, like Xilinx, rely on a LUT or LUT-based logic element with an output flip-flop. Others have a combinatorial logic cell, such as QuickLogic's large input, multiplexer-based logic cell with an output flip-flop. The programmable interconnects range from fuse and antifuse to memory-based connections, using SRAM, flash, or EEPROM configuration memory. The trend in higher-end FPGAs has been toward hierarchical routing, implementing a mix of nearest-neighbor, local, and global routing resources.
As serial-data-input clock rates climb, FPGAs will work with wider and wider datapaths needed to "parallelize" the serial input for processing using its slower internal clocks. FPGA cells' bit widths are slowly starting to widen to handle larger datapaths. For example, the latest Xilinx FPGA, the Virtex II, has widened its Configurable Logic Blocks (CLBs). It integrates a stack of four slices interfacing to a switch matrix. Making up the basic slice are two function generators, each containing a four-input LUT, a multiplexer, and a flip-flop.
Similarly, Agere's ORCA Series 4, designed for datapath implementations, has a wide logic implementation. The basic logic element is the programmable function unit (PFU), which is organized as twin sets of four four-input LUTs and four latches/flip-flops, with a spare flip-flop for the PFU.
Today's CPLDs have gone beyond combinatorial logic and state-machine implementations. They're often used to configure and operate on datapaths, such as multiplexing signal lines, or to operate on datapath elements at bus speeds. Some CPLD densities are pushing 500,000 system gates and higher. Cypress' Delta39K CPLD integrates up to 505,000 gates (3840 macrocells) with up to a 672-kbit cluster and a 168-kbit channel memory, plus 512 I/O pins. The CPLD clocks in at 154 MHz, and even higher for less dense parts.
CPLDs also supply fast switching for datapath elements. For instance, Lattice's ispLSI 2000VE family of CPLDs deliver 3-ns pin-to-pin switching, used to multiplex and operate on moving data. The CPLD's internal logic clocks at up to 300 MHz and supports up to 192 macrocells.
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