Electronic Design

Scalable Compute System Cranks Out 11 GFLOPS

This software-configurable processor array delivers a high-performance, flexible solution for media, imaging, and communications signal processing.

The prevailing challenge in any media-processing or communications system is obtaining enough compute cycles to execute the desired algorithms in real time. But the cost of that solution can't exceed whatever level is targeted by system designers. Often, this rules out a custom-designed ASIC unless volumes run over a million units per year. It also likely rules out very large FPGAs because their chip areas make them very expensive, even in large volumes.

Designers at Cradle Technologies think they have the answer: Put plenty of easily configurable computational and I/O elements and an abundant amount of local memory on one chip. Dubbed Soft Silicon, this fits well in media-processing and communications applications stream processing. Also, many compute-engines working in parallel can efficiently perform linearly scalable packet processing.

To get the most out of the configurability, though, Cradle's designers developed a powerful suite of programming tools and a rich library of software intellectual property. The tools include a multiprocessing debugger and an application profiler. These two work together to quickly and deterministically interrogate multiple system functions that are operating simultaneously. One key aspect of the company's programming model is the support of standards-based ANSI C and GNU libraries—a familiar environment for many system developers.

Cradle's first configurable and scalable Soft Silicon device release is a shared-memory multiple-instruction/multiple-data compute solution that can deliver an aggregate throughput of 11 GFLOPS.

Though it's a general-purpose chip, the company plans to initially release two firmware implementations that can be downloaded to the chip. The first, known as the media-processing engine, targets streaming-media-type applications and includes algorithms for MPEG4 codecs and various audio codecs. The second firmware release, the enhanced communications engine, aims at communication systems that use packet-based data.

Samples of the software scalable system-on-a-chip, with a clock speed of 150 MHz, are immediately available. They cost about $100 in moderate volume.

See associated figure

Cradle Technologies
www.cradle.com

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