Electronic Design

Scalable Processors Add Fuel To Network Data Rates

Able to handle packets and threads, two network processor families scale to meet network needs.

By providing intelligent packet processing and rapidly processing more network threads, two network processor families reduce the cost and complexity of line cards and other network infrastructure systems. Raza Microelectronics' Orion and XLR lines integrate functions that previously required multiple chips.

Processing packets to provide value-added services is a key issue for network systems. Orion takes that challenge head on with its TR30xx family (Fig. 1). The chips offer eight 10/100-Mbit/s Ethernet ports, two 10/100/1000-Mbit ports (all with autonegotiation support), and up to four OC-3/12 (STM-1/4) network ports (or optionally, a fabric interface with up to an STS-48/STM-16 bandwidth).

The packet processors include powerful packet traffic-management capabilities. This brings quality-of-service support for up to 2048 individual user flows and support for up to 1024 virtual switches with resource isolation between Ethernet local-area-network (LAN) domains. The virtual switch section includes integrated support for MAC tables with fully automated learning and aging, support for 802.1Q virtual LANs, and up to 256 ports per virtual switch.

Also on-chip, multistage scheduling/shaping for minimum bandwidth guarantees per user flow. Supported protocols include MPLS, Ethernet, PPP, HDLC, X.86, GFP, and multiple encapsulation levels. Also in the mix is Sonet/SDH support for up to 192 virtual connections. Integrated clock recovery allows direct connection to low-cost optical transceivers, and there is simultaneous support for low-order and high-order VCX circuits.

The chips integrate a cross-connect fabric with a 2.544-Gbit/s bandwidth. This enables support for pass-thru time-division multiplexing (TDM) as well as AU-3 and AU-4 SDH payload mapping schemes, including TUG-3. The Orion packet processors include multiple data framing and tagging features, plus data and TDM expansion ports. A simple microprocessor interface that handles 16-
or 32-bit data and 17-bit addresses and operates at 66 MHz provides a direct connection to control processors such as the Motorola MPC860/8260 and other standard CPUs.

Orion has four versions: the TR2010, 3010, 3020, and 3040. The latter two house more Gigabit Ethernet and data ports, so they can handle more user flows. Providing legacy T1/E1 and T3/E3 support, the TR1010 and 1040 "Pegasus" processors round out the system support.

The XLR thread-processor line consists of single-chip programmable solutions for high-performance secure networking, content, and services processing. Based on multiple enhanced MIPS64 64-bit CPUs, the scalable architecture eliminates the need for microcoding or proprietary scripting (Fig. 2).

Depending on the horsepower needed, Raza plans to offer six versions of the XLR processor. Chips will pack two, four, or eight enhanced MIPS64 CPU cores. These cores are four-way multithreaded engines that hold 512 kbytes or 1 or 2 Mbytes of level 2 cache (error-checking and correction included). As a result, the high-end versions can implement up to 32 virtual processors, with each processor handling one thread.

All versions can run at clock speeds of up to 1.5 GHz. In addition, applications can switch between threads every clock cycle. Each MIPS64 core also contains 32 kbytes each of instruction and data cache. The instruction cache uses parity to catch errors, while the data cache employs error checking and correction. The cores also include software enhancements to improve the thread processing.

Programming the processors in C or C++ accelerates application development. Developers also can leverage widely available development tools for the MIPS instruction-set architecture. In addition to the multiple processors, designers incorporated network acceleration hardware in the form of a packet distibution engine for line-rate processing, flexible packet tagging, queuing and management, and a TCP checksum verification/generation capability.

To support security applications, a dedicated security processor that can handle DES, 3DES, AES, ARC4, SHA-1, MD5, and RSA/DH encryption/decryption algorithms was integrated on the XLR chips. One, two, or four crypto cores allow the security engine to deliver throughputs from 2.5 to 10 Gbits/s of bulk encryption/decryption. The security engine also includes a random number generator and RSA/DH exponentiation for inline IPsec, SSL, and other security applications.

To reduce the number of required external support chips, the XLR processors include up to two SPI-4.2 interfaces (16-port), two 10-Gbit/s Ethernet MACs (XGMII), up to four 10/100/1000-Mbit/s Ethernet MAC 8-bit HyperTransport links (3.2 Gbytes/s aggreate throughput), a PCI-X 64-bit interface, a pair of configurable 800-MHz dual-channel DRAM controllers, and a quad-data-rate SRAM interface. Additional integrated support includes a PCMCIA card interface, dual I2C ports, dual 16550 UART ports, a 32-bit general-purpose I/O interface, and a four-channel DMA controler. Such a setup reduces overall system cost, power, and pc-board real estate.

Interconnecting the on-chip resources to each other is a high-speed distributed interconnect that provides 384 Gbits/s of nonblocking bandwidth. Also on the chip is a fast messaging network that delivers scalable communications between key processing and I/O elements.

The highest-performance XLR processors, the XLR732 and 532, pack eight CPU cores. They also feature 2 Mbytes of L2 cache, a 10-Gbit/s security engine, four 10/100/1000-Mbit Ethernet ports, and two 10-Gbit ports. Both include HyperTransport and PCI-X interfaces as well.

The XLR716 and 516 pack four CPU cores, 1 Mbyte of L2 cache, and four 1-Gbit/s capable ports. Both the XLR732 and 716 also include two 10-Gbit ports. The XLR 532 and 516 do not have the 1-Gbit ports. Lastly, the XLR508 and 308 have just two CPU cores, just 512 kbytes of L2 cache, and just four or three 1-Gbit Ethernet ports, respectively. The lowest-cost version is housed in a 786-pin package, while the higher-performance versions all come in 1605-pin packages due to the higher I/O and memory requirements.

Samples of the Orion and XLR chips are available now (Fig. 3). In volume, prices for the Orion processors range from $200 to $500 apiece. Pegasus chips go for $40 to $75 each. Prices for the XLR chips range from $150 to $850 apiece.

Raza Microelectronics Inc.
www.rmi.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish