Electronic Design

Self-Timed Interconnect Network Eases SoC Designs

A chip-area interconnection (CHAIN) scheme developed by Silistix promises reduced power consumption and simpler system-on-a-chip (SoC) design by eliminating many problems associated with traditional global bus architectures. Generated by the CHAINworks design and synthesis tool suite, the CHAIN interconnect fabric is a self-timed, packet-based interconnect network that manages the flow of data between IP cores on a chip.

The fabric's self-timing eliminates dependence on the edges of a system clock. Sent in packets, data then can flow quickly as possible between stages. results in less power consumption since traffic load now dictates power, not a fixed clock distribution network.

Clock domains in the CHAIN fabric don't depend on a system clock. These domains don't have to be a multiple of the system clock either. Furthermore, the interconnect fabric can be tuned to meet specific throughput, area, and power targets.

A new way of looking at the on-chip interconnection issues, the CHAIN fabric simplifies the design effort. It provides faster timing closure, easy design scaling, IP vendor independence, and protocol independence. (AHB and APB support are available now, and AXI and OCP-IP support are on the roadmap.)

Silistix-provided adapters can link existing synchronous IP blocks to the CHAIN fabric, permitting designers to continue using existing IP. Adding initiators or targets doesn't affect the rest of the design, making the overall SoC design very scalable.

The CHAINworks software tool suite fits within the existing EDA design tool flows (see the figure). Designers can use it to craft and synthesize CHAIN fabrics for multimillion-gate SoCs. The suite supports multiple unrelated clock domains and dynamic clock frequency control, and it eliminates frequency-balancing issues.

The suite includes three elements: CHAINdesigner, CHAINcompiler, and CHAINlibrary. The designer tool is used to design and implement custom CHAIN networks for simulation as well as for netlist synthesis. It lets designers optimize the on-chip interconnects to achieve the best balance between performance, area, and power. CHAINdesigner also permits designers to create custom topologies. And, it generates a SystemC model of the interconnect.

The compiler tool leverages the library of clock-independent building blocks and assemblies, synthesizes the network fabric, and adds design-for-test elements into the fabric. It also generates a structural netlist.

The CHAIN networks' self-timing virtually eliminates system timing violations. But it can't be adequately expressed by or constructed from existing register-transfer-level tools, prompting the need for the specialized compiler tool. Contact the company for licensing terms.

Silistix Inc.
www.silistix.com

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