Electronic Design
Shift Register Generates Multiple Clocks From PWM Signal

Shift Register Generates Multiple Clocks From PWM Signal

This circuit transforms a pulse-width-modulation (PWM) signal into non-overlapping clock signals, whose number depends on the length of a shift register. These clock signals can be used to power up different loads in a predetermined sequence, as is sometimes necessary in complex systems.

The circuit uses D-flip-flops, two of which are included in each SN74LVC74 IC. The example circuit generates eight independent clock signals (Fig. 1). A pulse generator or a microcontroller can provide the PWM input, which can vary in frequency and duty cycle.

The circuit shown can accept signals with 1% to 99% duty cycles. A circuit for an actual clock system must account for the operating conditions specified in the datasheets for the chosen logic family. Also, the value of pull-up resistors R3-R10 will depend on the circuit’s operating speed.1 The PWM signal is fed to the clock inputs of the flip-flops as well as to the output-enable inputs of the gates inside of IC3 and IC6. As a result, a clock pulse is generated at the eight clock outputs when the PWM pulse is also present.

To ensure that the pulse widths of the clock outputs are similar to the duty cycle of the PWM signal, the Q output signals of the different flip-flops are fed to the respective driver gates. The gates in IC3 and IC6 (SN74LVC125) are three-state drivers. Pull-up resistors R3-R10 guarantee a correct signal level at the eight clock outputs when these gates are in three-state status.

The Q output of the first flip-flop drives the D input of next flip-flop, and so on, forming the shift register. The Q output of the last flip-flop in the chain is connected to the D input of the first one, closing the ring structure of the shift register. By adding or subtracting flip-flops and three-state gates to/from the structure and including an appropriate connection between the first and last flip-flop, the designer can create different numbers of clocks as needed.

Connecting low or high signal levels, respectively, to the PR and CLR inputs of individual flip-flops during the shifting sequence will determine whether the circuit will generate a shifting pulse at the eight output clocks, more parallel shifting pulses, or a special selected pulse scheme. The pulses in the selected scheme will shift also with each step of the PWM signal. After power-up, a Power-on Reset signal must be fed to the respective circuit input. A signal from the PWM signal-generating microcontroller or another signal source used for control purposes can be applied.

Figure 2 shows the results from a system supplying six clock pulses, which are generated by the PWM signal provided by a microcontroller (channel 1). Channels 2 through 4 display the resulting signals at three of the circuit’s clock outputs that follow each other according to the selected sequence. The results indicate a clear relationship between the PWM signal and the clock output signals.

REFERENCE

1. Das TTL-Kochbuch, G. Becke and E. Haseloff, Texas Instruments Deutschland

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