Although individual process advances such as strained silicon or silicon-on insulator (SOI) can pump up performance, it will take more than one boost to meet future system-on-a-chip (SoC) application demands. Thus, strained silicon or strained silicon germanium also can be used with SOI technology for a three-in-one enhancement over basic silicon. Already, chip manufacturers are producing a few high-performance communication and processor products that employ strained silicon.
The obstacles impeding fabrication of transistors in the silicon represent only one segment of the overall challenge to create the next generation of high-performance ICs. Other sticking points include interconnection of all transistors and ensuring that they're all testable.
As chip manufacturers continue to transition to 90-nm process rules, metallization systems are moving from aluminum to copper. Various versions of damascene copper deposition have let chip manufacturers stack many levels of metal on top of the silicon, providing an abundant amount of interconnect for the hundreds-of-million to billion-plus transistors.
About half a decade ago, any design that incorporated five or more levels of metal was pushing its luck concerning chip yield. Today, field-programmable gate arrays and other chips routinely come with up to 10 levels of metal interconnect. Even more levels of metal may be used in future chips. How far can it go? Well, it's a matter of yield from the manufacturing line.
Each mask layer can potentially introduce errors that will affect how many good chips can be harvested from each wafer. With too many layers, the number of chips will drop and the cost per chip will skyrocket. For now, though, 10 or so layers will handle most chip designs.
But the metallization system does present limitations due to the metal itself, or the routing of the metal lines. Most of today's on-chip interconnect is set up in an X-Y grid. To go from point A to point B across a complex chip, the wiring must snake through the grid like a taxi driver looking for open lanes during rush hour. That's one reason why so many layers are needed, providing more opportunities for the wires to weave through.
However, the weaving path taken by the wire can be much longer than the direct (almost line-of-sight) distance to the other point (such as a diagonal line might produce). This introduces more resistance and capacitance, and in general can degrade overall circuit performance.
An alternative to the X-Y grid is now becoming widely available. Known as the X-Initiative, the new metallization approach uses the X-Y grid but supplements it with the ability to use angular lines (458) in the fourth and fifth metal layers. These lines can shorten the length of many interconnections, which significantly reduces the number of wires and layer-to-layer vias. In turn, overall chip performance gets another boost.
One of the first chips produced using the X-Initiative approach-the TC90400XBG-comes from Toshiba Corp. The chip, which incorporates functions for digital media and home entertainment systems, was fabricated using 130-nm design rules. Compared to previous company products with equivalent complexity, the X-architecture implementation yields a chip that's approximately 11% faster and 10% smaller in random-logic area.
No matter how fast or small the chip is at the end of the production line, the big question is whether or not it works. Numerous capable VLSI test systems are available, but a litany of factors may still prevent the test system from verifying full functionality.
In addition, because many high-complexity processors used in computation and networking contain lots of memory, no vendor wants to throw away a processor due to a few bad bits. So memory redundancy often is incorporated, and this memory must be thoroughly tested and repaired.
Many memory blocks are often "buried" in the architecture, though, and they can't be directly accessed through the I/O pins. Often, the same holds true for other functions incorporated in a host of chip designs.
Coming to the rescue are advances in built-in self-test and repair (STAR) schemes, such as those offered by Virage Logic and several other vendors. The third generation of Virage's STAR system for embedded memory will support a mix of repairable and non-repairable memory blocks. It will ultimately shorten integration into the chip design from weeks to days.