Soft Peripherals + Hard Cores = Reconfigurable SoCs

Designers can incorporate an array of peripherals into asics and platform systems-on-a-chip. but custom designs have very high upfront costs, making them practical only when chip production runs are counted in the millions. Reconfigurable SoCs, however, have minimal upfront costs, providing developers with an alternative to custom SoCs and standard processors with external peripherals.

Reconfigurable SoCs are sometimes called platform FPGAs. While some products incorporate conventional FPGAs, a number of other options permit reconfigurable custom peripherals by employing specialized building blocks. All result in a chip with a standard CPU core that uses custom peripherals.

This reconfigurable approach offers significant advantages. It reduces design costs because changes can be made immediately to the chip during development. Chip simulation becomes less of an issue because the real hardware is available immediately. In the field, bug fixes and upgrades can be more extensive as significant portions of the hardware can be altered, not just the application code. Finally, reconfigurable systems open up design options.

For example, an MP3 player/recorder doesn't usually operate in both modes at the same time, and the support hardware for playback and recording differ. A reconfigurable system can set up a block of logic to handle MP3 decoding for playback and change this block into an encoder once the device has been set up for recording.

The main disadvantage is cost. Often, the reconfigurable portion of a chip is much larger than the fixed components, such as the processor core or built-in peripherals, increasing chip prices. So reconfigurable SoCs are used in final products when the number of units sold is low, or the cost of the chip is a small fraction of the product price. They also are popular for prototyping because the core CPU and fixed peripherals are well defined. Building a custom ASIC or SoC based on a reconfigurable prototype is relatively easy.

Reconfigurable systems aren't new, but alternatives like large FPGAs tend to be more expensive than some others (see "FPGAs? Yes... Maybe," above). Additionally, FPGAs can find it hard to compete with a fixed-CPU implementation because the FPGA must provide more general logic support. This makes a fixed device considerably smaller in size and lower in cost. The fixed device can also be better optimized for speed and power consumption.

Reconfigurable systems shouldn't be confused with configurable processor designs like those available from ARC and Tensilica (see "Custom CPUs Are Not Reconfigurable," p. 54). They also differ from Ubicom's SX 50/75 MIPS Communications Controller, which uses Virtual Peripherals. In this case, designers trade off CPU performance for peripheral support by emulating hardware logic in software and toggling I/O ports directly. Basic analog devices can be simulated using external hardware.

Designing a system for an FPGA is no simple matter, especially when it comes to CPUs. Developers implementing reconfigurable SoC solutions limit the custom configuration by keeping the CPU design fixed and frequently using some standard peripherals.

For these reasons, reconfigurable SoCs are popular with developers. With numerous reconfigurable chips on the market, a range of applications is covered (see the table). Examples of these chips include Altera's Excalibur, QuickLogic QuickMIPS, Cypress PSoC (Programmable System on a Chip), Triscend A7 and E5, Atmel's FPSLIC (Field-Programmable System-Level IC), and Xilinx's Virtex II Pro. QuickMIPS and Virtex II Pro address networking and communication, with QuickMIPS working well in routers/gateways. Virtex II Pro, with its high-speed serial links, targets higher-end equipment.

The Atmel FPSLIC, Cypress PSoC, and Triscend E5 target microcontrollers. They all have 8-bit processor cores, and only the E5 doesn't incorporate on-chip flash memory. The Triscend A7 packs an ARM7 processor with a peripheral architecture that's almost identical to its little brother, the E5. ARM processors are very popular in portable applications, and the A7 delivers this support with reconfigurable peripherals.

A more detailed examination of each product highlights their differences and features. In general, each has one or more fixed CPU cores. JTAG debug support is popular. RAM, flash, and fixed peripherals are optional. Devices without flash typically result in a two-chip solution. The amount of flash memory is based on application requirements.

QuickLogic QuickMIPS: As MIPS is a staple in embedded systems, the MIPS32 4Kc was an ideal choice for the heart of QuickLogic's QuickMIPS (Fig. 1). The processor runs at 133 MHz in the 0.25-µm version and at 175 MHz in the 0.15-µm version. It supports MIPS DSP extensions. On-chip data and code caches are four-way set associative and 16 kbytes in size. The memory controller handles off-chip flash and RAM, although 16 kbytes of RAM are on-chip. The advanced high-performance bus (AHB) is used for device interconnects.

The fixed peripherals highlight the target market for QuickMIPS. Incorporating a pair of 10/100 Ethernet controllers and a pair of high-speed serial controllers, it's perfect for VoIP (voice over Internet protocol) gateways and other telecommunications devices. The reconfigurable portion makes the chip ideal for industrial control applications.

The QL901M version consists of a logic array of 72-by-28 elements for a total of 2016 logic cells. There also are 36 RAM blocks with a total of 82,944 bits of storage. Also, the logic array can use the chip's 18 embedded computational units (ECUs), which include 8-by-8 multipliers and 16-bit adders.

An array of high-speed LVDS serial/deserializers (SERDES) complements the conventional general-purpose I/O ports. Each line supports up to 1 Gbit/s.

Cypress PSoC: In its PSoC family, Cypress has a range of products. All include flash memory and RAM, making them ideal single-chip microcontroller solutions (Fig. 2). The PSoC employs a custom 8-bit processor with enhancements like an 8-by-8 multiplier with a 32-bit accumulator.

The PSoC is unique in two areas. First, it has no fixed peripherals. Instead, all I/O must use the configurable blocks. Second, it includes analog and digital blocks for analog chores. Other reconfigurable solutions can emulate some analog functions with external components. Otherwise, external analog logic must be included in the system design.

To make peripheral selection easier, the chip configuration IDE contains a wide range of standard analog and digital peripherals, including analog-to-digital converters and serial ports. The IDE can also handle multiple configurations in a single design, simplifying mode switches from one peripheral configuration to another.

Triscend A7 And E5: Triscend's first FastChip design was the E5, a microcontroller based on the 8051 (Fig. 3). It gained some on-chip building blocks as the newer A7, which is based on the ARM7 processor.

The configurable system-logic (CSL) matrix incorporates cells with flip-flops that can be set up as dual-port memory. The cells also comprise dedicated circuitry for adders, multiplexers, and counters, making the array more sophisticated than a basic FPGA or PLD.

High-speed DMA devices have access to on-chip RAM and off-chip memory. There are one or two UARTs on chip but all other peripherals are implemented via the CSL matrix, which is also accessible via DMA.

Atmel FPSLIC: Atmel's FPSLIC combines the company's popular AVR RISC processor with SRAM and an Atmel FPGA (Fig. 4). The FPGA incorporates Atmel's FreeRAM design, which sprinkles memory throughout the gate array. This is independent of the SRAM. The memory is accessible directly by the AVR processor. Each FPSLIC device has a pair of UARTS and some timers as built-in peripherals. The remaining peripheral support must be implemented via the FPGA.

Xilinx Vertex II: Wrapping a single processor core with a reconfigurable matrix is one thing. Linking up to four 300-MHz PowerPC 405 cores to 16 3.125-Gbit/s RocketIO channels licensed from Mindspeed is another. That's what happens in Xilinx's high-end Virtex II (Fig. 5).

This product line targets high-end communications. The high-speed serial channels can deal with demanding protocols like InfiniBand, 10-Gbit Ethernet, Serial ATA, and 3GIO. Channel bonding is supported. The standard SelectI/O Ultra interfaces handle up to 840 Mbits/s of data.

The PowerPC processors are major powerhouses. They include 16-kbyte caches for code and data and incorporate an MMU that supports variable page sizes. The programmable matrix includes features such as dedicated 18- by 18-bit multiplier blocks and fast carry chains. These are ideally suited for high-speed packet processing.

Altera Excalibur: Altera doesn't try to hide the fact that its Excalibur is a large programmable logic device (PLD)—up to 1 million gates—with some fixed components tacked on one side of the array (Fig. 6). Of course, this doesn't detract from the fact that the processor is a 200-MIPS ARM9. It includes ARM's trace support plus a JTAG interface for debugging. The ARM9 works with the ARMv4T instruction set, including the 16-bit Thumb extensions. The processor has 8-kbyte data and code caches and an MMU.

Some other fixed components are a UART and some timers, an interrupt controller, and an external memory interface that supports flash, SRAM, and DDR SDRAM. Just add some flash memory to get this system up and running.

One interesting aspect of the design is a mixture of dual-port and single-port RAM. They're linked to the AMBA bus to the processor. The second port of the dual-port RAM is dedicated to the PLD.

Take The Plunge: One great thing about reconfigurable SoCs is that it doesn't cost a bundle to try them out. Developer kits often run a few hundred dollars. They let complete designs be implemented and tested on boards that come with the kit.

I have worked with a number of these kits, and they're relatively easy to use. The major investment is the time it takes to learn what peripherals are available and how they're selected, placed, and configured. Simple peripheral configurations are easy, but more complex configurations take a while to design and debug.

Learning about the core processor and fixed peripherals isn't a quick process either. Many designers will already have expertise on standard processor cores like the 8051 or ARM found in some reconfigurable SoCs. Others will employ custom CPU architectures, so a C or C++ compiler will have to be available to hide the architecture from developers. Otherwise, additional time will be needed to learn the architecture and its idiosyncrasies.

Development kits enable a designer to be up and running within a day. Relatively sophisticated systems can start operating within a week. This permits more time for application development versus the fine tuning of a hardware design that must then be committed to a custom SoC.

Reconfigurable SoCs can be more complex to use than custom or standard SoCs if dynamic runtime reconfiguration is used, as noted earlier with the MP3 player/recorder example. Care must be taken when reconfiguring the system. Outputs must be controlled properly and other parts of the programmable matrix have to be retained, assuming that only part of the system changes at once. Usually, the development tools simplify this chore. But changing hardware can lead to some interesting debugging problems that wouldn't occur in a fixed-hardware environment.

Usually, the matter of implementing reconfigurable SoCs boils down to the price of the chip. This cost can be easily compared to custom and standard SoC alternatives, as well as the option of using a standard microcontroller with external peripherals or an FPGA to employ the necessary custom logic. While the costs may not be justified for large-scale production runs in the millions, reconfigurable SoCs fare well in limited production runs, prototyping, or beta testing.

Keep in mind that configurable SoCs can also provide an upgrade path. Many system designs won't use 100% of the configurable logic, so new hardware-based features can be added in the future by making use of unused reconfigurable logic. Alternatively, lower-cost versions of a reconfigurable chip with just enough memory and peripheral logic can be used in production if they are available.