EE Product News

Structured ASICs

Heard about Structured ASICs but aren't sure exactly what they are and how to use them. In this edition of REFRESH! EEPN contributing editor, Andrew Leone, gives you a guided tour of these devices and tells you which vendors supply them.

























 By Andrew Leone, Contributing Editor







A Structured ASIC is a type of integrated circuit that contains blocks of logic,

called "tiles." These tiles reside in the die ready to be connected in a customizable format. Also, logic gates are available for designers to implement their own IP into the Structured ASIC. Logic gates and also interconnects are constructed by the completion of metal layers.



Figure 1 shows the typical block diagram of a Structured ASIC. Structured ASICs can include embedded CPUs and DSPs, blocks of embedded memory, analog circuitry and PLLs. Other blocks can exist depending on the vendor and device family.




      In addition, there are user-defined customizable gates. These gates allow the designer to integrate his own IP into the design as well as create interconnects for the hardened blocks. The manufacturing process is shortened, since only one to five layers of metal need to be added to the wafer in order to complete a custom design (see Figure 2).




 How do they compare to ASICs and FPGAs?



The turn-around-time for Structured ASICs is shorter compared to Standard Cell ASICs. Test, power, signal integrity, clock trees, and IP integration are built into the Structured ASIC’s architecture

      Structured ASICs reduce the steps needed to implement a design compared to Standard Cell ASICs. Test development and insertion, power design and analysis, and signal integrity analysis are eliminated because these steps have been for the most part standardized for Structured ASIC devices. Steps such as IP integration and memory insertion also have been eliminated. The main benefit of eliminating these steps is to

reduce design time and reduce resources needed to implement a particular design.

      As for FPGAs, these devices have been widely used in the last decade for quick turn around time, limited design effort and little to no NRE. FPGAs, though, have limitations compared to Structured ASICs (see the Table). FPGAs typically have lower performance, higher power consumption, limited logic integraton, low comparable density, and higher unit cost.



Structured ASICs vs. FPGAs




Structured ASIC








Power Consumption

Very High






Logic Integration








Very Low






Unit Cost

Very High






Timing Iterations









      Much time may also have to be exerted on optimization of FPGA code to try and get Standard Cell ASIC performance. The main difference in performance lies in the fact that there are limitations on the FPGA’s logic cell and routing architecture. The interconnect delay, for example, causes performance differences. FPGAs do not optimize the routing lengths from transistor to transistor. The routing elements bring larger delays to the signal paths, in turn increasing die size and therefore increasing delays.

      A Structured ASIC’s optimized logic and performance as well as efficient routing translates to lower power consumption than FPGAs. FPGAs need more power to program the part on start-up and also have to implement routing, look-up tables and logic. Much power is needed for internal set-up and power up of the FPGA device.

      Due to the significant overhead of programmable routing, even the largest FPGA provides relatively low logic integration. Much of the FPGA resources are taken up by routing and other internal issues as opposed to actual customized logic; this results in a larger die size. These larger die sizes cause lower yields and rising manufacturing costs. The per unit cost associated with FPGAs make it ideal for proof of concept and low volume applications, whereas the Structured ASIC allows for smaller die size and lower cost for higher volumes.



What are they USED FOR?


Structured ASICs meet the requirements of a myriad number of medium- to high-volume applications (1K to 100K typically) that don’t demand cutting edge performance or the highest density. Structured ASICs offer vendor-specific and vendor tested design flows that can minimize risk, lower costs and complexity, while at the same time maintaining the best performance and maximum density.




Many Structured ASIC vendors have partnered with tool manufacturers to make sure their devices are fully utilized and optimized for the designer’s benefit. The specific Structured ASIC device and the vendor-specific design methodology are interwoven. Figure 3 shows a typical design flow for the LSI Rapid Chip product. As shown, LSI Logic uses its Rapid Worx tool in conjunction with Synplicity’s Amplify Synthesis product. The benefit is that a large portion of time and resources can be spent on the customization of the part as opposed to the checking and layout of the device.

      In contrast, if a designer tried to use another toolset not specified by the Structured ASIC vendor, the performance and density of the Structured ASIC couldn’t be fully realized. In addition, the design cycle would take weeks or even months longer. The joint development of tools by Structured ASIC vendors and EDA tools manufacturers has in effect closed the gap even further between Structured ASICs and Standard Cell ASICs. If a designer was to use a generic set of tools in a Structured ASIC design, the tool would more than likely overuse or underuse the circuit elements and throw off timing and utilization.

      In Structured ASICs, there is a pre-defined floorplan, pre-defined die size, pre-defined placement for hardened macros, and clocking constraints are set. One of the largest issues is timing closure, which can be eliminated with the specific design tools and pre-set architecture. Structured ASICs also have a power grid already laid out in the device’s lower layers. The power consumption is a known factor before manufacturing and characterization.

      ASIC designers want to minimize risk with a particular design. They want to know if a device will work prior to wafer manufacturing. The Structured ASIC vendor and tool manufacturer offer designers reduced risk, cost, and complexity while maximizing performance, density and time to market.




There are many different types of Structured ASICs on the market. The following gives a short summary of what is available.

      FPGA conversions have been a popular design option in the market for some time. Altera and AMI offer FPGA to Structured ASIC conversion products.

      Altera has Hardcopy and Hardcopy II. These Structured ASICs are meant to be designed using an Altera FPGA then converted to their Structured ASIC products, the Hardcopy and Hardcopy II. They have given this as an option so their customers can reduce the cost of the high-priced FPGA. AMI’s approach is similar with their XPressArray and XPressArray II families. They are targeting designs that use high-priced Altera and Xilinx FPGAs. The main purpose behind the conversion is cost reduction. They offer pin-for-pin compatible packages and they offer densities from 49K gates to 4.8 million gates.

      LSI Logic offers the Rapid Chip Platform ASICs. LSI calls the parts in their product families "slices." Slices are standard block logic elements with customizable logic gates. The slices include the Integrator and the Xtreme. The Integrator is for low-cost designs and Xtreme is geared for high-speed SERDES and other high-performance applications. Their densities range from 400K to 5 million gates. LSI also offers diverse IP including ARM 7, 9 and 11 CPU cores.

      Chipx offers five different families of Structured ASICs. Their products range from 0.6 µm with the lowest gate count of 23K gates up to the highest gate count of 1.8 million gates at 0.13 µm geometry. Chipx’s new product family, the CX6000, offers hardened IP of USB 2.0 OTG. In addition, they offer validated, synthesizable processors.

      NEC and Fujitsu are traditional semiconductor manufacturers that have entered the Structured ASIC market. NEC offers their ISSP products, which have geometries of 0.15 µm and 90 nm. Fujitsu has the AccelArray family. These devices are designed using a 0.11 µm geometry. They have the Mega platform and the Giga Platform families. The performance is up to 333 MHz and offers four customizable metal layers. The Mega platform is for reduced cost designs and the Giga platform is for high-performance SERDES implementations. Fujitsu also offers ARC and ARM CPU IP as well as networking, USB and wireless IP. The impetus for these companies to offer Structured ASIC products is that the cost of NRE and development resources in the smaller geometries is unbelievably expensive and hence higher risk. Structured ASICs are way for NEC and Fujitsu to offer cutting edge geometry while limiting risk.

      eASIC has the most unique product of all. This company developed a cross between an FPGA and Structured ASIC. The interconnects or routing on the ASIC are completed by either a Direct Ion Beam on the wafer or by metal mask implementation. The Direct Ion Beam also takes one-tenth of the time of a full metal mask process. The Direct Ion Beam completes the specified design vias in the ASIC. The custom logic section is handled by look-up tables similar to FPGAs. This part of the design is reprogrammable and is loaded on the eASIC product at power-up. The performance and utilization is similar to other Structured ASICs, but allows for even quicker turn around time.





There are two main design tool vendors that have embraced the Structured ASIC market. Synplicity and Magma have aligned themselves with Structured ASIC vendors in order to ensure quicker turn around and offer maximized performance.

      Synplicity offers the Amplify family of EDA tools for Structured ASIC products. They support, through specific versions, ISSP from NEC, Rapid Chip from LSI Logic, and Hardcopy from Altera. They also have a standard "ASIC" version that supports Faraday, AMI and Chipx. The key to Symplicity’s tool is timing consistency. The tool has an understanding of the silicon design rules and architecture specific to the Structured ASIC vendor. The tool maintains efficient and accurate timing, utilization and routing. This allows for a consistent and known result from when the design is handed-off to the vendor for production. It minimizes the unknown.

      Magma has an RTL to GDSII design flow. Their Blast SA product handles floorplanning synthesis, mapping and placement. The Blast Create SA is an RTL to placed gate design tool and the Blast Fusion SA is a netlist to GDSII chip implementation system specifically for Structured ASICs. These tools allow for the optimization of the Structured ASIC device. Magma has partnered with Faraday and Chipx to support their products with the Magma SA flow.





In summary, Structured ASICs offer the following:

1. Density, capacity, speed and power consumption comparable to Standard Cell ASICs

2. Low NRE and development effort

3. Shorter design schedule and production lead times

4. Ability to make changes to design without huge mask costs



Andrew Leone is a regular contributor to EEPN. He earned his BEE from Johns Hopkins University



Company: EEPN

Product URL: Click here for more information


Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.