Structured ASICs Now Pack Up To 2 Million Programmable Gates

The latest version of the XPressArray structured ASIC family improves density by 40% over the previous XPressArray series. The XPA-HD runs at clock speeds of up to 200 MHz and offers up to 2 million programmable gates and up to 1.4 Mbits of embedded memory. The XpressArrays are designed with FPGA conversions in mind, so customers can create prototypes using existing FPGA tools. An available cell library includes delay-locked loops, phase-locked loops, and RAM blocks that match the blocks offered by the FPGA vendors. Prototypes can be shipped in less than 10 days after customer sign-off of validated configuration. Nonrecurring engineering charges range from $80,000 to 200,000, while unit prices can be as little as $6 apiece in annual quantities of 50,000 units.