Electronic Design

System-On-A-Chip Toolbox Helps Perfect Design Recipe

New SoC building blocks and tools can assist in planning chip designs, buying precious time to add your "special sauce" to the mix.

System design today hinges on two key steps: your ability to adequately select and analyze the available building blocks, and then stirring in the "special sauce" that makes your product unique. The more aware you are of the available building blocks you can trust, the more time you can spend perfecting the flavor of your sauce.

To assist the chef, here's a list of the latest intellectual-property (IP) offerings, the tools to help with the IP selection process, and some recommended reading. Let's start with the most important stage of system-on-a-chip (SoC) recipes: the available ingredients.

RECENT SOCIP INGREDIENTS
There's always a host of new and exciting IP ingredients to discuss. If you're proficient with Google, you can find most of the pre-built IP blocks to assist with preparation of the seven-course SoC meal. A few of this year's IP blocks really stand out.

Faraday Technology's Ultra-Wideband (UWB) Medium Access Controller (MAC) IP solution offers a high transfer rate and low pin count. By integrating Faraday's UWB MAC IP into your SoC design, it's possible to hit over 200 Mbits/s of throughput—double the typical throughput achieved by most of today's application-specific standard-product (ASSP) offerings.

Higher speeds have been achieved with a Peripheral Component Interface (PCI), but also at a higher pin count than what may be available on complex SoC designs. Faraday's solution incorporates an industry-standard MAC-PHY Interface (MPI) for communications between your SoC and an external UWB physical-layer (PHY) IC. For more information on UWB, see "The Year Of Ultra-Wideband" at www.electronicdesign.com, ED Online 12045.

If you require high-density logic, nonvolatile-memory solution IP, consider Kilopass Technology's Extra Permanent Memory (XPM). It's available for 90-nm standard (XPM90G) and low-power (XPM-90LP) CMOS process technology implementations.

The XPM offerings deliver field-programmable memory solutions ideally targeted at digital content protection and digital-rights-management schemes, or other types of applications requiring encryption keys. Further applications include firmware and calibration parameters, hardware configuration, and boot code storage.

Need a PCI Express Gen 2 controller IP block? GDA Technologies' GPEX-2 IP is optimized for latency, link utilization, power consumption, and reliability. It also comes in a small footprint. Target applications include networking and telecommunications with end-point, root complex, switch, and bridge implementations.

GPEX-2 offers a flexible, scalable architecture that's simple to customize. It supports 32-, 64-, and 128-bit data widths, and can be configured with one, two, four, eight, or 16 lanes per link. It's independent of application logic, PHY designs, and target technology. And with PCISIG compliance, this verified solution will get you up and running quickly.

If you're searching for standard CMOS-based IP implementations of, for instance, a pulse-width-modulation controller, an asynchronous sample-rate converter, or a digital-to-analog converter targeted for audio applications, consider Anagram Technologies. This company recently introduced a family of products built using what it calls Digital PureLogic SoC IP.

Based on digital filtering and delta-sigma technology, the family suits low-power applications as well as applications requiring a high level of integration, along with the precise reconstruction of analog signals. The family is fully CMOScompatible, so auto place-and-route software can fully control the layout of any Digital PureLogic IP block.

Such control provides the traditional benefits of minimizing digital noise coupling without the device-matching issues typical of other implementations required to achieve good linearity. Target applications include compact, low-cost, and low-power high-fidelity multimedia; automotive; and consumer products.

For a listing of security-related IP, see "Has Anyone Seen My Data?" at ED Online 15387. For the basics of converting FPGA designs to ASICs, see "Avoid The Bird Flu With Proper FPGA Migration" at ED Online 16143.

A TEST RECIPE
If you're involved in a complex design— multiple cores and complex IP blocks, several buses, and multiple clocks—you probably wish you had a window that provides a view into your design for real-time debugging and performance optimizations.

But real-time debugging and performance tweaks require access into the bowels of the chip while it's under a typical load in the system. To make matters worse, trace data must be filtered to a manageable and relevant quantity.1

There is light at the end of the tunnel, though, thanks to IP from Infineon (available through IPextreme) called MultiCore Debug Solution (MCDS). MCDS enables you to execute cycle-accurate tracing of a selected core, along with buses and other signals within the chip, all non-intrusively, in real time, and under a typical "real world" load.

MCDS supports limitless debug targets, where a target could be a processor core, an IP block, a signal bus, or any set of signals. Once integrated into your SoC, MCDS collects and stores trace data from the blocks you specify and then dumps the data to software for debug and analysis (Fig. 1).

During the observation phase, target trace information is collected from specified sources, such as instruction pointers, address and data buses, process IDs, and so on for the target(s) to be analyzed and debugged. But since you probably only want to collect data under certain conditions, you can control when data is collected by specifying trigger conditions in much the same way you would with a logic analyzer.

The traces are stored as compressed messages in memory and can be accessed through a typical interface, such as JTAG. The beauty of this implementation is in its simplicity, because not one pin needs to be added to support this functionality.

The ability to debug in real time and under conditions not replicable in a comfy lab environment is invaluable, especially in situations where it isn't possible to connect probes or when doing so could easily affect the outcome. This setup also alleviates the burden of attempting to recreate such an environment.

IF I HAD A HAMMER
The IP industry has been busy building some interesting tools to assist with the creation of SoC masterpieces. For example, Chip Estimate Corp. offers one-stop shopping with a Web site dedicated to helping you find IP to fit your needs and tools to help you plan your SoC. Visitors to the site can perform a filtered search for IP, browse available IP by type, and bookmark favorite IP each time they find an interesting block.

Also, you can use Chip Estimate's InCyte tool to help plan SoC designs and try various "what-if" scenarios (Fig. 2). The tool enables you and your team to assess the performance and cost of using IP blocks and manufacturing data. Using processor, power, and technology node tradeoffs, you will be in a better position to make informed decisions about your SoC early in the design phase.

InCyte takes a high-level design specification, including gate count, target performance, external bus connection information, target IP blocks, and the system's memory configuration, as input. After doing a quick analysis, it delivers a report that contains highly accurate estimates of die area, performance, power, leakage, yield, target package, and production cost.

"New chip planning technologies deliver early insight into the implications of IP, process technology, and architectural decisions before the traditional IC design flow begins. Accurately predicting die size, power, leakage, performance, and packaged chip cost, these tools minimize the risk of having to cancel projects later, wasting scarce designer resource and missing target market windows," says Casey Jones, vice president of marketing at Chip Estimate.

"New methodologies that feed design data from implementation systems back into chip planning promise to add fast and accurate cost-awareness throughout traditional EDA design flows," adds Jones. For more information, see "Cost Aware Design Methodology" at www.electronicdesign.com, Drill Deeper 16432.

The Fabless Semiconductor Association's Hard IP Quality Risk Assessment tool enables IP vendors, SoC designers, independent device manufacturers, and semiconductor foundries to all communicate more efficiently. This macrodriven spreadsheet tool also saves time by providing the information required to buy and integrate the target IP at intervals ranging from pre-purchase to licensing to design and manufacturing.

By using this tool, you can compare similar IP blocks from various vendors and come to understand the "hidden" licensing costs. Once all of the licensing costs are understood, you will be in a better position to make an informed decision about which IP block will best suit your application's needs.

The tool's output is a risk assessment profile chart that will ultimately empower SoC designers to understand an IP vendor's design methodology. It also assesses the risks of using the IP according to various criteria, such as design, integration, verification, target process technology, documentation, reliability, and test.

And according to Chip Estimate president Adam Traidman, the Fabless Semiconductor Association and Chip Estimate are working closely together to bring designers a plethora of easily accessible IP data including quality information so they can make informed decisions about which IP they will be designing in.

SOME LIGHT RECIPE READING
Some interesting white papers discuss new approaches to SoC designs, which help in the IP procurement process.

Toshiba's Power-Saving Clock-Gating Technique is an Inseparable Part of SoC Design discusses the use of clock-gated designs to achieve both low power and improved timing performance. Additionally, it includes some valuable clock-gating pointers as well as pitfalls to avoid.

Another paper from Toshiba, Impact of Multiple-Voltage Domain (MultiVDD) Design Implementation on Large, Complex SoCs, gets into the low-power benefits of multi-VDD designs, achieving a low-power design while delivering needed performance and functionality. But beware that such designs require considerable planning and upfront analysis, especially with respect to the SoC architecture.

For information on identifying common issues encountered during IP negotiations, see The Current State Of Semiconductor Intellectual Property (SIP) Licensing from the Fabless Semiconductor Association.

Self-timed Interconnect Enables True IP Reuse, by David Lautzenheiser of Silistix, discusses methods to simplify and accelerate IP reuse processes. It also talks about the data flow between IP cores and how replacing global clock-based bus systems with self-timed logic to improve intra-core communications leads to enhanced IP reuse capabilities.

Fully Digital Implemented Phase Locked Loop, written by Michael Gude and Gerriet Mueller of Cologne Chip, provides an approach to designing phase-locked loops. The process uses only digital cell libraries to overcome the problems typical of integrating traditionally analog technology into ever-shrinking CMOS process technologies. The paper also serves up information on verifying functionality using a purely digital simulator.

Reference
1. Multi-Core Debug Solution IP: SoC Software Debugging and Performance Optimization, May 2007, Albrecht Mayer, Infineon Technologies AG, Harry Siebert, Infineon Technologies AG, Christian Lipsky, IPextreme Inc.

NEED MORE INFORMATION?
Anagram Technologies
www.anagramtech.com/products/ip
Chip Estimate Corp.
www.chipestimate.com
Cologne Chip
www.colognechip.com
Fabless Semiconductor Association
www.fsa.org
Faraday Technology
www.faraday-tech.com
GDA Technologies
www.gdatech.com/ip
Infineon
www.infineon.com
IPextreme
www.ip-extreme.com
Kilopass Technology
www.kilopass.com
Silistix
www.silistix.com
Toshiba
www.toshiba.com/taec/adinfo/socworld

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