Third-Gen Fab Process Will Permit 80-GHz All-Digital Transceiver

Using its third generation of superconducting microelectronics technology, Hypres Inc. has successfully tested ICs featuring a critical current density of 20 kA/cm². Several rapid single flux quantum (RSFQ) digital circuits were built and tested, including a 325-GHz digital frequency divider, a 4-bit binary counter, and various I/O elements. The successful tests pave the way for the company to build an all-digital transceiver able to operation in excess of 80-GHz clock speeds, according to Hypres.

In digital superconductivity, critical current density directly impacts clock speed. The higher the critical current density, the faster the chip and the higher the performance of all-digital transceivers. The company had previously implemented a 4.5 kA/cm² critical current density process to develop an all-digital transceiver running at a 40-GHz clock rate. These chips use Josephson junctions approximately 1.5 by 1.5 microns in size. The new 20-kA/cm² process will enable smaller, faster Josephson junctions and therefore, an 80-GHz clock.

Hypres developed the new process with support from the U.S. Office of Naval research (ONR). The company has received numerous contracts from the ONR in its development of the all-digital transceiver.