A three-chip set has been introduced as a support solution for the 184-pin, PC200/PC266, 72-bit-wide registered double-data-rate (DDR) SDRAM memory module. A full interface solution for this DDR dual in-line memory module (DIMM), the chip set helps meet critical timing requirements in memory subsystem designs for servers and workstations. It fully complies with the JEDEC DDR SDRAM registered DIMM design.
This set consists of the FMS7857 phase-locked loop (PLL) clock driver, the SSTV16857 registered buffer, and the FM34W02 serial-presence detector EEPROM. It supports the DDR SDRAM's ability to operate at twice the system frequency, transferring data on both edges of the clock.
A zero-delay clock buffer, the FMS7857 PLL clock driver synchronizes signals to each memory chip. Operating at a 2.5-V VDD from 95 to 170 MHz, it features low skew and jitter.
The SSTV16857 registered buffer is a 14-bit register that performs address and control buffering. It features an SSTL-2-compatible I/O structure, a 2.5-V VDD, and differential SSTL-2-compatible clock inputs.
A 2-kbit, two-wire bus interface EE-PROM, the FM34W02 supports serial-presence detection circuitry in memory modules. It also lets the CPU determine the capacity and the electrical characteristics of the memory devices it contains.
The FMS7857 and SSTV16857 are available in sample and production quantities. The FM34W02 is offered in sample quantities. Production quantities will be available in the fourth quarter.
Packaged in a 48-pin TSSOP, the FMS7857 costs $4.00. The SSTV16857 is supplied in a 48-pin TSSOP and costs $4.25. Packaged in both 8-pin TSSOPs and SOICs, the FM34W02 costs $0.80. All prices are for 1000-unit quantities.
Fairchild Semiconductor, 333 Western Ave., South Portland, MN 04106; (888) 522-5372; fax (972) 910-8036; www.fairchildsemi.com.