Rule number one for designers of portables: Optimize the power usage in embedded applications for long battery life and efficient cooling. A number of options exists to reach this goal, whether it's powering down idle components within a system or creating a more efficient hardware design.
Following in that mold is Philips' LPC3180 (Fig. 1). Based on the 32-bit ARM926EJ architecture, it's designed for battery operation using a reduced-leakage system design. The processor includes Java and IEEE-754 vector floating-point hardware support.
Such support is important for two reasons. First, hardware support typically is more power-efficient than a software implementation. Second, processing can be completed sooner thanks to vector floating-point support, opening up the possibility that the system or portions of it could be shut down to save power.
This often is achievable in "cyclic" types of systems. Alternatively, the processor can run continuously but at a lower clock frequency. Running slowly usually equates to reduced voltage and current requirements, as is the case with the LPC3180.
The LPC3180, which operates at a peak frequency of 208 MHz, can deliver up to 228 MIPS. The 1.2-V core voltage's ultra-low-power mode runs at 0.9 V. Even with the floating-point engine enabled, the LPC3180 can run at 13 MHz while consuming only 7.1 mA—even with the vector-processing unit turned on (see the table). Interface voltages measure 3.3 and 1.8 V.
At 13 MHz, the chip can deliver 14.3 DMIPS (Dhrystone millions of instructions per second). This translates to 2.24 DMIPS/mW, enabling the processor to accomplish a number of tasks at low clock rates.
Turning on the instruction cache requires a minimal increase in power (0.45 mA at 13 MHz). At the same time, the cache will boost performance by 10%. It's a good tradeoff overall, and the programmer can make that call. Each data cache and the vector-processing unit can be powered down individually. The same is true for the on-chip peripherals and controllers.
The chip supports the usual power-conservation methods, including phase-locked-loop (PLL) switching, clock division, a real-time-clock (RTC) wakeup interrupt, and low-power mode during processor idle. The RTC and a small amount of on-chip SRAM support battery backup.
The LPC3180's vector floating-point system supports single-and double-precision data. Single-precision operations require only a single cycle, with the exception of operations like divide and square root. Double-precision operations take twice as long.
Routed through three separate floating-point pipelines. this performance supports out-of-order execution. Generally, the floating-point unit improves performance fivefold. It also reduces the need for a floating-point runtime library, which is typically larger than 27 kbytes.
Moving data around efficiently can be just as important as processing complex numbers. That's why Philips implemented a bus matrix (AHB-lite) instead of a single-bus structure (Fig. 2).
The bus matrix permits simultaneous transfers, though a particular device can be part of only one bus access at a time. For example, by using the matrix, the data cache can access SRAM at the same time the instruction cache accesses DRAM. In the meantime, the DMA unit moves information to or from a peripheral.
LPC3180 ARM ARCHITECTURE
The rest of the LPC3180 architecture resembles other ARM9 designs. It includes a 32-kbyte instruction and 32-kbyte data cache. The memory management unit (MMU) lets the processor run protected-mode operating systems such as Linux.
The LPC3180 packs 64 kbytes of on-chip SRAM and features an on-chip boot ROM. External memory interfaces include support for 1.8-V Mobile double-data-rate SDRAM, NAND flash, SD flash cards, and Sony Memory Stick flash cards. For debugging support, there's a standard E-ICE JTAG interface. Moreover, 6 kbytes of embedded-trace-buffer (ETB) memory is integrated on-chip.
On-chip peripherals include a pair of pulse-width-modulation (PWM) timers, eight serial ports (one with IrDA support), a pair of I2C ports, an SPI port, USB 2.0 full-speed host support along with On-The-Go support, a keyscan port, and 45 parallel I/O ports shared with other peripherals. A 10-bit analog-to-digital converter (ADC) with a 3-V range resides on the analog side.
Included are an on-chip 32-kHz clock and PLL support for higher frequencies. Accuracy comes in under 2%, which should suffice for UART communications. An external clock or crystal also can be used.
The LPC3180 will support Linux and a range of other operating systems. C/C++ compilers for the chip are available from ARM, IAR, and Green Hills Software, in addition to gcc.
Based on 90-nm technology, the LPC3180 comes in a 320-pin TFBGA package. Pricing starts at $7.10.